公开(公告)号：US20160179169A1

公开(公告)日：2016-06-23

申请号：US15049236

申请日：2016-02-22

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Daniel C. Murray ,  Wei-Han Lien

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.

Abstract translation: 在一个实施例中，系统可以包括多个处理器和配置成在各个操作点之间切换处理器的自动功率状态控制器（APSC）。 操作点可以由编程到APSC中的数据描述，并且APSC可以包括可编程的寄存器，其具有从所描述的操作点中识别处理器的目标操作点的目标操作点请求。 描述操作点的数据还可以包括在操作点处可能同时活动的处理器的数量是否受限制的指示。 基于指示和有效处理器的数量，APSC可以以减小的操作点覆盖所请求的操作点。 在一些实施例中，数字功率估计器（DPE）可以监视处理器的操作，并且可以在检测到高功耗时调节处理器。

公开(公告)号：US09311100B2

公开(公告)日：2016-04-12

申请号：US13735694

申请日：2013-01-07

Applicant: Apple Inc.

Inventor： Sandeep Gupta ,  Shyam Sundar ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Conrado Blasco-Allue

IPC: G06F9/00 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/30072 ,  G06F9/3806 ,  G06F9/3848

Abstract: A circuit for implementing a branch target buffer. The branch target buffer may include a memory that stores a plurality of entries. Each entry may include a tag value, a target value, and a prediction accuracy value. A received index value corresponding to an indirect branch instruction may be used to select one of entries of the plurality of entries, and a received tag value may then be compared to the tag value of the selected entries in the memory. An entry in the memory may be selected in response to a determination that the received tag does not match the tag value of compared entries. The selected entry may be allocated to the indirect instruction branch dependent upon the prediction accuracy values of the plurality of entries.

Abstract translation: 用于实现分支目标缓冲器的电路。 分支目标缓冲器可以包括存储多个条目的存储器。 每个条目可以包括标签值，目标值和预测精度值。 对应于间接分支指令的接收到的索引值可以用于选择多个条目中的一个条目，然后将接收到的标签值与存储器中所选条目的标签值进行比较。 响应于接收到的标签与被比较的条目的标签值不匹配的确定，可以选择存储器中的条目。 所选择的条目可以根据多个条目的预测精度值分配给间接指令分支。

公开(公告)号：US09304573B2

公开(公告)日：2016-04-05

申请号：US13924164

申请日：2013-06-21

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Daniel C. Murray ,  Wei-Han Lien

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.

Abstract translation: 在一个实施例中，系统可以包括多个处理器和配置成在各个操作点之间切换处理器的自动功率状态控制器（APSC）。 操作点可以由编程到APSC中的数据描述，并且APSC可以包括可编程的寄存器，其具有从所描述的操作点中识别处理器的目标操作点的目标操作点请求。 描述操作点的数据还可以包括在操作点处可能同时活动的处理器的数量是否受限制的指示。 基于指示和有效处理器的数量，APSC可以以减小的操作点覆盖所请求的操作点。 在一些实施例中，数字功率估计器（DPE）可以监视处理器的操作，并且可以在检测到高功耗时调节处理器。

公开(公告)号：US09280471B2

公开(公告)日：2016-03-08

申请号：US14081549

申请日：2013-11-15

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Harshavardhan Kaushikkar ,  Gurjeet S. Saund ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Sukalpa Biswas ,  Brian P. Lilly ,  Shinye Shiu

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0822 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract translation: 与SoC中的其他代理程序共享代理的私有缓存的系统，处理器和方法。 SoC中的许多代理除了SoC的共享缓存和内存之外还有一个专用缓存。 如果代理的处理器关闭或以小于满容量运行，代理的私有缓存可以与其他代理共享。 当请求代理产生存储器请求并且存储器请求丢失在存储器高速缓存中时，存储器高速缓存可以在单独的代理的高速缓存中分配存储器请求，而不是在存储器高速缓存中分配存储器请求。