公开(公告)号：US09389860B2

公开(公告)日：2016-07-12

申请号：US14035467

申请日：2013-09-24

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30058 ,  G06F9/30072 ,  G06F9/3842 ,  G06F9/3848

Abstract: A method of predicting a backward conditional branch instruction used in a vector partitioning loop includes detecting the first conditional branch instruction that occurs after consumption of a dependency index vector by a predicate generating instruction. The dependency index vector includes information indicative of a number of iterations of the vector partitioning loop, and the conditional branch instruction may branch backwards when taken. The conditional branch instruction may then be predicted to be taken a number of times that is determined by the dependency index vector.

Abstract translation: 一种预测在向量分割循环中使用的反向条件分支指令的方法包括：通过谓词生成指令检测消耗依赖性索引向量后出现的第一条件分支指令。 依赖性索引向量包括指示向量分割循环的迭代次数的信息，并且条件分支指令可以在采取时向后分支。 然后可以将条件分支指令预测为由依赖性索引向量确定的次数。

公开(公告)号：US20150227369A1

公开(公告)日：2015-08-13

申请号：US14177399

申请日：2014-02-11

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/3824 ,  G06F9/3836

Abstract: In an embodiment, a processor may include a completion time prediction circuit. The completion time prediction circuit may be configured to track one or more aspects of previous instances of a vector memory operation, and may be configured to predict a completion time for a current instance of the vector memory operation. The prediction may be used by the issue circuit to schedule operations dependent on the vector memory operation, if any.

Abstract translation: 在一个实施例中，处理器可以包括完成时间预测电路。 完成时间预测电路可以被配置为跟踪向量存储器操作的先前实例的一个或多个方面，并且可以被配置为预测向量存储器操作的当前实例的完成时间。 发布电路可以使用该预测来根据向量存储器操作调度操作（如果有的话）。

公开(公告)号：US09009383B2

公开(公告)日：2015-04-14

申请号：US14331336

申请日：2014-07-15

Applicant: Apple Inc.

Inventor： Ian C. Hendry ,  Rajabali Koduri ,  Jeffry E. Gonion

IPC: G06F12/00 ,  G06F3/06 ,  G06F1/32 ,  G06F12/02 ,  G06F12/06 ,  G06F17/30 ,  G06F12/08

CPC classification number: G06F3/0647 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0673 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/0646 ,  G06F12/08 ,  G06F17/30147 ,  G06F2003/0697 ,  Y02D10/14 ,  Y02D50/20

Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.

Abstract translation: 提供了当存储器的一部分被激活或去激活时用于动态地映射和重映射存储器的系统，方法和设备。 根据实施例，电子设备可以包括几个存储器组，一个或多个处理器和存储器控制器。 存储体可以将数据存储在硬件存储器位置中，并且可以被独立地去激活。 处理器可以使用物理存储器地址请求数据，并且存储器控制器可以将物理地址转换为硬件存储器位置。 当第二数量有效时，存储器控制器可以使用第一存储器组的第一存储器映射功能和第二存储器映射功能。 当存储器组中的一个被禁用时，存储器控制器可以将数据仅从要被去激活的存储器组复制到存储体的有效剩余部分。

公开(公告)号：US20140289498A1

公开(公告)日：2014-09-25

申请号：US14218497

申请日：2014-03-18

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30192 ,  G06F9/345 ,  G06F9/3838

Abstract: Systems, apparatuses and methods for utilizing enhanced Macroscalar vector operations which take an enhanced predicate operand that designates the element width and which elements are to be processed. The element width and the number of elements per vector are determined at run-time rather than being defined in the architectural definition of the instruction. This enables additional parallelism when processing smaller-sized data. The instruction performs the requested operation on the elements specified by the enhanced predicate, assuming an element-width also specified by the enhanced predicate, and returns the result as a vector of elements of the same element width.

Abstract translation: 用于利用增强的宏观矢量操作的系统，装置和方法，其采用指定元素宽度和要处理哪些元素的增强谓词操作数。 元素宽度和每个向量的元素数量在运行时确定，而不是在指令的体系结构定义中定义。 这可以在处理较小尺寸的数据时实现额外的并行性。 指令对增强谓词指定的元素执行所请求的操作，假设由增强谓词指定的元素宽度，并将结果作为元素宽度相同的元素的向量返回。

公开(公告)号：US20140289496A1

公开(公告)日：2014-09-25

申请号：US14218287

申请日：2014-03-18

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30192 ,  G06F9/345 ,  G06F9/3838

Abstract: Systems, apparatuses and methods for utilizing enhanced macroscalar predicate operations which take enhanced predicate operands that designate the element width and which elements are to be processed. The element width and the number of elements per vector are determined at run-time rather than being defined in the architectural definition of the instruction. This enables additional parallelism when processing smaller-sized data. The instruction performs the requested operation on the elements specified by the enhanced control predicate, assuming an element-width also specified by the enhanced control predicate, and returns the result as an enhanced predicate of the same element width.

Abstract translation: 用于利用增强的宏观谓词操作的系统，装置和方法，其采用指定元素宽度和要处理哪些元素的增强谓词操作数。 元素宽度和每个向量的元素数量在运行时确定，而不是在指令的体系结构定义中定义。 这可以在处理较小尺寸的数据时实现额外的并行性。 指令对增强控制谓词指定的元素执行所请求的操作，假设由增强控制谓词指定的元素宽度，并将结果作为相同元素宽度的增强谓词返回。

公开(公告)号：US08583904B2

公开(公告)日：2013-11-12

申请号：US13628781

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/302 ,  G06F9/305

CPC classification number: G06F8/4441 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30072

Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a negation operation dependent upon the input vector and the control vector.

Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收输入向量和控制向量的指令。 执行的指令还可以使处理器执行取决于输入向量和控制向量的否定操作。

公开(公告)号：US20130111193A1

公开(公告)日：2013-05-02

申请号：US13717480

申请日：2012-12-17

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F8/4441 ,  G06F9/3001 ,  G06F9/30036

Abstract: In the described embodiments, a processor generates a result vector when executing a RunningShiftForDivide1P or RunningShiftForDivide2P instruction. In these embodiments, upon executing a RunningShiftForDivide1P/2P instruction, the processor receives a first input vector and a second input vector. The processor then records a base value from an element at a key element position in the first input vector. Next, when generating the result vector, for each active element in the result vector to the right of the key element position, the processor generates a shifted base value using shift values from the second input vector. The processor then corrects the shifted base value when a predetermined condition is met. Next, the processor sets the element of the result vector equal to the shifted base value.

Abstract translation: 在所描述的实施例中，当执行RunningShiftForDivide1P或RunningShiftForDivide2P指令时，处理器生成结果向量。 在这些实施例中，在执行RunningShiftForDivide1P / 2P指令时，处理器接收第一输入向量和第二输入向量。 然后，处理器从第一输入向量中的键元素位置处的元素记录基值。 接下来，当生成结果向量时，对于结果向量中的关键元素位置右侧的每个活动元素，处理器使用来自第二输入向量的移位值来生成移位的基值。 然后，当满足预定条件时，处理器校正偏移的基值。 接下来，处理器将结果向量的元素设置为移位的基本值。

公开(公告)号：US20130024671A1

公开(公告)日：2013-01-24

申请号：US13628781

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/302

CPC classification number: G06F8/4441 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30072

Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a negation operation dependent upon the input vector and the control vector.

Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收输入向量和控制向量的指令。 执行的指令还可以使处理器执行取决于输入向量和控制向量的否定操作。

公开(公告)号：US20130024651A1

公开(公告)日：2013-01-24

申请号：US13630596

申请日：2012-09-28

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F15/76

CPC classification number: G06F9/30036 ,  G06F8/441 ,  G06F8/4441 ,  G06F9/30032 ,  G06F9/30072

Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an operand vector, a selection vector, and a control vector are disclosed. The executed instructions may also cause the processor to perform a wrapping rotate previous operation dependent upon the input vectors.

Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收操作数向量，选择向量和控制向量的指令。 执行的指令还可以使得处理器执行包装，以取决于输入向量旋转先前的操作。

公开(公告)号：US12242396B2

公开(公告)日：2025-03-04

申请号：US18343125

申请日：2023-06-28

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Bernard J. Semeria

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/1027 ,  G06F21/52

Abstract: A memory permissions model for a processor that is based on the memory address accessed by an instruction as well as the program counter of the instruction. These permissions may be stored in permissions tables and indexed using the memory addresses of the instruction and the address of the memory locations that it accesses. Those indexes may be obtained from a page table in some cases. These memory permissions may be used in conjunction with other permissions, such as execute permissions and secondary execution privileges that are based on whether the instruction belongs to a particular instruction group.