公开(公告)号：US20170010655A1

公开(公告)日：2017-01-12

申请号：US14793778

申请日：2015-07-08

Applicant: Apple Inc.

Inventor： Muditha Kanchana ,  Erik P. Machnicki

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F12/0813 ,  G06F12/0822 ,  G06F12/0831 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A method and apparatus for power management of cache duplicate tags is disclosed. An IC includes a cache, a coherence circuit, and a duplicate tags memory that may store duplicates of the tags stored in the cache. The cache includes a number of ways that are separately and independently power controllable. The duplicate tags memory may be similarly organized, with portions that are power controllable separately and independently of others. The coherence circuit is also power controllable, and may be placed into a sleep mode when idle. The IC also includes a power management circuit. During operation, the cache may change power states and provide a corresponding indication to the power management circuit. Responsive to the indication, the power management circuit may awaken the coherence circuit if in a sleep state. The coherence circuit may then power manage the duplicate tags in accordance with the change in power state.

Abstract translation: 公开了一种缓存重复标签的电源管理方法和装置。 IC包括缓存，相干电路和可以存储存储在高速缓存中的标签的重复的重复标签存储器。 高速缓存包括单独和独立的功率可控的多种方式。 重复的标签存储器可以类似地组织，其中部分功率可以单独地并且独立于其它功能。 相干电路也是功率可控的，并且可以在空闲时被置于睡眠模式。 IC还包括电源管理电路。 在操作期间，高速缓存可以改变功率状态并且向电源管理电路提供相应的指示。 响应于指示，如果处于睡眠状态，则电源管理电路可唤醒相干电路。 然后，相干电路可以根据电源状态的变化来对重复标签进行电源管理。

公开(公告)号：US09317102B2

公开(公告)日：2016-04-19

申请号：US13733775

申请日：2013-01-03

Applicant: Apple Inc.

Inventor： Muditha Kanchana ,  Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Erik P. Machnicki ,  Seye Ewedemi

IPC: G06F1/32 ,  G11C5/14

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C5/144 ,  Y02D10/14

Abstract: Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.

Abstract translation: 公开了关于降低集成电路中的功耗的技术。 在一个实施例中，一种装置包括具有一组标签结构的缓存和电源管理单元。 功率管理单元被配置为响应于被断电的高速缓存而将重复的一组标签结构断电。 在一个实施例中，高速缓存被配置为向电力管理单元提供高速缓存是否包括有效数据的指示。 在这样的实施例中，功率管理单元被配置为响应于缓存指示高速缓存不包括有效数据的高速缓存来关闭高速缓存。 在一些实施例中，重复的标签结构集合位于被配置为保持高速缓存和存储器之间的一致性的相干点内。

公开(公告)号：US20160049207A1

公开(公告)日：2016-02-18

申请号：US14459466

申请日：2014-08-14

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Erik P. Machnicki ,  Gilbert H. Herbeck

IPC: G11C17/18 ,  G11C7/20 ,  G11C17/16

CPC classification number: G11C7/20 ,  G11C17/16 ,  G11C2029/0407 ,  G11C2029/4402

Abstract: In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode.

Abstract translation: 在一个实施例中，装置可以包括多个电路块，多个保险丝和电路。 电路可以被配置为响应于从关闭模式转换到第一操作模式来确定多个保险丝中的每一个的状态。 可以在第一操作模式中启用第一数量的电路块。 电路还可以被配置为根据多个保险丝中的一个或多个保险丝的状态并从第一操作模式转换到第二操作模式来初始化第一数量的电路块。 可以在第二操作模式中使能小于第一数量的第二数量的电路块。 电路还可以被配置为将表示多个保险丝的子集的状态的数据存储到在第二操作模式中启用的第一存储器中。

公开(公告)号：US09201821B2

公开(公告)日：2015-12-01

申请号：US13629509

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Josh P. de Cesare ,  Manu Gulati

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: A system and method for maintaining accurate interrupt timestamps. A semiconductor chip includes an interrupt controller (IC) with an interface to multiple sources of interrupts. In response to receiving an interrupt, the IC copies and records the value stored in a main time base counter used for maintaining a global elapsed time. The IC sends an indication of the interrupt to a corresponding processor. Either an interrupt service routine (ISR) or a device driver requests a timestamp associated with the interrupt. Rather than send a request to the operating system to obtain a current value stored in the main time base counter, the processor requests the recorded timestamp from the IC. The IC identifies the stored timestamp associated with the interrupt and returns it to the processor.

Abstract translation: 一种用于保持精确中断时间戳的系统和方法。 半导体芯片包括具有多个中断源的接口的中断控制器（IC）。 响应于接收到中断，IC复制并记录存储在用于维持全局经过时间的主时基计数器中的值。 IC向对应的处理器发送中断指示。 中断服务程序（ISR）或设备驱动程序请求与中断相关联的时间戳。 处理器不是向操作系统发送请求以获得存储在主时基计数器中的当前值，而是从IC请求记录的时间戳。 IC识别与中断相关联的存储时间戳，并将其返回给处理器。

公开(公告)号：US09024699B2

公开(公告)日：2015-05-05

申请号：US13746247

申请日：2013-01-21

Applicant: Apple Inc.

Inventor： Kleanthes G. Koniaris ,  Erik P. Machnicki ,  Shane J. Keil

IPC: H03K3/64

CPC classification number: H03K3/64

Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

Abstract translation: 用于基于参考时钟产生输出时钟的各种技术。 本公开涉及基于参考时钟信号产生输出时钟信号。 在一个实施例中，一种方法包括：使用从控制电路接收的信息，使用输入时钟信号的第一数量的边缘或输入时钟信号和第二不同数量的边缘来产生输出时钟信号。 在本实施例中，控制电路的运行频率小于输入时钟信号的频率。 接收到的信息可以针对输出时钟信号的脉冲来指示是否应该使用第一数量的边缘或第二数量的边缘来生成脉冲。 在某些情况下，第二数量的边可以是第一数量的边加上一个边。 第一和第二数量的边缘可以是可编程的数量。

公开(公告)号：US20140203884A1

公开(公告)日：2014-07-24

申请号：US13746247

申请日：2013-01-21

Applicant: APPLE INC.

Inventor： Kleanthes G. Koniaris ,  Erik P. Machnicki ,  Shane J. Keil

IPC: H03L7/099 ,  H03K3/64

CPC classification number: H03K3/64

Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

Abstract translation: 用于基于参考时钟产生输出时钟的各种技术。 本公开涉及基于参考时钟信号产生输出时钟信号。 在一个实施例中，一种方法包括：使用从控制电路接收的信息，使用输入时钟信号的第一数量的边缘或输入时钟信号和第二不同数量的边缘来产生输出时钟信号。 在本实施例中，控制电路的运行频率小于输入时钟信号的频率。 接收到的信息可以针对输出时钟信号的脉冲来指示是否应该使用第一数量的边缘或第二数量的边缘来生成脉冲。 在某些情况下，第二数量的边可以是第一数量的边加上一个边。 第一和第二数量的边缘可以是可编程的数量。

公开(公告)号：US20140201578A1

公开(公告)日：2014-07-17

申请号：US13739554

申请日：2013-01-11

Applicant: APPLE INC.

Inventor： Alexei E. Kosut ,  Erik P. Machnicki

IPC: G06F11/07

CPC classification number: G06F11/0757 ,  G06F11/0736

Abstract: Due to software bugs, hardware bugs, power fluctuations, cosmic rays, and various other causes, computing systems may from time to time enter various types of error states. This disclosure relates generally to the field of watchdog timers configured to take corrective action when a computing system enters such an error state. In various embodiments, this disclosure provides systems, methods, apparatuses, and computer-readable media for multi-tier watchdog timers. Such multi-tier watchdog timers may be configured to take different levels of corrective action at different times and/or under different conditions.

Abstract translation: 由于软件错误，硬件错误，功率波动，宇宙射线和各种其他原因，计算系统可能会不时地输入各种类型的错误状态。 本公开一般涉及被配置为当计算系统进入这样的错误状态时采取校正动作的看门狗定时器的领域。 在各种实施例中，本公开提供了用于多层看门狗定时器的系统，方法，装置和计算机可读介质。 这种多层看门狗定时器可以被配置为在不同时间和/或在不同条件下采取不同级别的校正动作。

公开(公告)号：US20210341317A1

公开(公告)日：2021-11-04

申请号：US17372764

申请日：2021-07-12

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F13/16 ,  G06F1/3293 ,  G06F1/3206 ,  G06F1/3287

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US10261894B2

公开(公告)日：2019-04-16

申请号：US15447328

申请日：2017-03-02

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G06F12/02 ,  G06F12/06 ,  G06F1/32 ,  G06F3/06 ,  G06F9/44 ,  G06F13/16 ,  G06F13/40 ,  G11C11/406 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/4401 ,  G06F13/42

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US10048720B2

公开(公告)日：2018-08-14

申请号：US15831732

申请日：2017-12-05

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Kiran B. Kattel ,  Manu Gulati

IPC: G06F1/12

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.