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公开(公告)号：US20250006674A1
公开(公告)日：2025-01-02
申请号：US18497585
申请日：2023-10-30
Inventor： Cyprian Emeka Uzoh , Oliver Zhao , Gabriel Z. Guevara , Dominik Suwito , Rajesh Katkar
IPC: H01L23/00
Abstract: A semiconductor element is provided with a micro-structured metal layer over conductive features of a hybrid bonding surface. The micro-structured metal layer comprises fine metal grain microstructure, such as nanograins. The micro-structured metal layer can be formed over the conductive features by providing a metal oxide and reducing the metal oxide to metal. The micro-structured metal layer can be formed selectively if the metal oxide is formed by oxidation. When directly bonded to another element, the micro-structured metal layer forming strong bonds at the bonding interface can substantially reduce annealing temperature.
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公开(公告)号：US20250006672A1
公开(公告)日：2025-01-02
申请号：US18379053
申请日：2023-10-11
Inventor： Cyprian Emeka Uzoh , Gaius Gillman Fountain, JR.
IPC: H01L23/00
Abstract: A first conductive feature of a first substrate is bonded to a second conductive feature of a second substrate. The first conductive feature is formed by depositing a conductive base layer on the first substrate, the first substrate having an opening formed therein, recessing the conductive base layer in the opening, and depositing a conductive surface layer on the recessed conductive base layer. Hybrid bonding of the first substrate to the second substrate is performed without use of an intervening adhesive to connect the first conductive feature and the second conductive feature.
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33.发明授权公开(公告)号：US12176263B2
公开(公告)日：2024-12-24
申请号：US18620753
申请日：2024-03-28
Applicant: Adeia Semiconductor Bonding Technologies Inc
Inventor： Belgacem Haba , Cyprian Emeka Uzoh , Rajesh Katkar
IPC: H01L23/46 , H01L23/00 , H01L23/34 , H01L23/373 , H01L23/48 , H01L23/498 , H01L23/24
Abstract: The present disclosure provides for integrated cooling systems including backside power delivery and methods of manufacturing the same. An integrated cooling assembly may include a device and a cold plate. The cold plate has a first side and an opposite second side, the first side having a recessed surface, sidewalls around the recessed surface that extend downwardly therefrom to define a cavity, and a plurality of support features disposed in the cavity. The first side of the cold plate is attached to a backside of the device to define a coolant channel therebetween. The cold plate includes a substrate, a dielectric layer disposed on a first surface of the substrate, a first conductive layer disposed between the first surface and the dielectric layer, a second conductive layer disposed on a second surface of the substrate, and thru-substrate interconnects connecting the first conductive layer to the second conductive layer.
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公开(公告)号：US20240387439A1
公开(公告)日：2024-11-21
申请号：US18784724
申请日：2024-07-25
Inventor： Belgacem Haba , Laura Wills Mirkarimi , Javier A. DeLaCruz , Rajesh Katkar , Cyprian Emeka Uzoh , Guilian Gao , Thomas Workman
Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.
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公开(公告)号：US20240379539A1
公开(公告)日：2024-11-14
申请号：US18782629
申请日：2024-07-24
Inventor： Cyprian Emeka Uzoh , Gaius Gillman Fountain, JR. , Jeremy Alfred Theil
IPC: H01L23/522 , H01L23/00 , H01L23/29 , H01L23/31
Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.
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Patent Agency Ranking
公开(公告)号：US20240312951A1
公开(公告)日：2024-09-19
申请号：US18183768
申请日：2023-03-14
Inventor： Cyprian Emeka Uzoh , Jeremy Alfred Theil , Gaius Gillman Fountain, JR. , Belgacem Haba , Rajesh Katkar
IPC: H01L23/00 , H01L21/027 , H01L21/56 , H01L23/12 , H01L25/16
CPC classification number: H01L24/80 , H01L21/0273 , H01L21/561 , H01L23/12 , H01L24/03 , H01L24/08 , H01L24/96 , H01L25/162 , H01L25/167 , H01L2224/0345 , H01L2224/03452 , H01L2224/03831 , H01L2224/03845 , H01L2224/08145 , H01L2224/80011 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H01L2224/96 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043
Abstract: An element includes a substrate and a surface layer on the substrate. The surface layer includes at least one first region comprising an optically transparent and electrically insulative first material and at least one second region at least partially embedded in the at least one first region. The at least one second region comprises an optically transparent and electrically conductive second material.
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公开(公告)号：US20240304593A1
公开(公告)日：2024-09-12
申请号：US18179126
申请日：2023-03-06
Inventor： Cyprian Emeka Uzoh
IPC: H01L23/00 , H01L25/00 , H01L25/065
CPC classification number: H01L24/80 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05647 , H01L2224/06181 , H01L2224/08145 , H01L2224/80009 , H01L2224/80013 , H01L2224/80357 , H01L2224/80379 , H01L2224/80895 , H01L2224/80896 , H01L2224/80906 , H01L2224/94 , H01L2224/97 , H01L2225/06565 , H01L2924/01006 , H01L2924/01014 , H01L2924/04642 , H01L2924/0504 , H01L2924/0544 , H01L2924/05494 , H01L2924/059
Abstract: Disclosed herein are processes and methods for direct bonding. In some embodiments, the process includes providing an element having a dielectric bonding surface and one or more conductive features exposed at the dielectric bonding surface, where the dielectric bonding surface has a planarity suitable for direct bonding. The process also includes, after providing the element, exposing the dielectric bonding surface to the products of a water vapor plasma prior to direct bonding the element.
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公开(公告)号：US12068278B2
公开(公告)日：2024-08-20
申请号：US18148369
申请日：2022-12-29
IPC: H01L23/00 , H01L21/02 , H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/683 , H01L21/78 , H01L23/31 , H01L25/00 , H01L25/065
CPC classification number: H01L24/83 , H01L21/02076 , H01L21/3085 , H01L21/31116 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3185 , H01L25/0657 , H01L25/50 , H01L21/3065 , H01L2221/68327 , H01L2221/68354 , H01L2221/68368 , H01L2224/83013 , H01L2224/83031 , H01L2224/83895 , H01L2224/83896
Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.
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公开(公告)号：US12046571B2
公开(公告)日：2024-07-23
申请号：US18058693
申请日：2022-11-23
Inventor： Cyprian Emeka Uzoh , Jeremy Alfred Theil , Liang Wang , Rajesh Katkar , Guilian Gao , Laura Wills Mirkarimi
IPC: H01L23/00
CPC classification number: H01L24/26 , H01L24/03 , H01L24/09 , H01L24/27 , H01L24/30 , H01L24/83 , H01L2224/08257 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028
Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
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40.发明公开公开(公告)号：US20240222315A1
公开(公告)日：2024-07-04
申请号：US18148332
申请日：2022-12-29
Inventor： Cyprian Emeka Uzoh
IPC: H01L23/00
CPC classification number: H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/94 , H01L2224/0345 , H01L2224/03614 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05166 , H01L2224/05184 , H01L2224/05186 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/08145 , H01L2224/8002 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/80906 , H01L2224/94 , H01L2924/04941
Abstract: An element, a bonded structure including the element, and a method of forming the same are disclosed. The bonded structure can include a first element having a first nonconductive field region and a first conductive feature. A surface of the first nonconductive field region and a surface of the first conductive feature at least partially defining a bonding surface of the first element. The first conductive feature includes a first portion and a second portion over the first portion and at least partially defines the surface of the first conductive feature. The first portion includes aluminum. The first conductive feature has a continuous sidewall along the first portion and the second portion. The second portion includes different metal composition from the first portion or comprising fluorine at the surface of the first conductive feature. The bonded structure can include a second element having a second nonconductive field region and a second conductive feature. A surface of the second nonconductive field region is directly bonded to the first nonconductive field region without an intervening adhesive along a bond interface and a surface of the second conductive feature is directly bonded to the second conductive feature without an intervening adhesive along the bond interface.
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