公开(公告)号：US20080256476A1

公开(公告)日：2008-10-16

申请号：US11934835

申请日：2007-11-05

Applicant: Joon-kyu SEO ,  Hyun-ki KIM ,  Jung-won LEE ,  Young-eun LEE ,  Hee-jeong BAE

Inventor： Joon-kyu SEO ,  Hyun-ki KIM ,  Jung-won LEE ,  Young-eun LEE ,  Hee-jeong BAE

IPC: G06F3/048

CPC classification number: G03G15/5016 ,  G03G15/502

Abstract: Provided are a copying apparatus and a user interface method for the same. The user interface method includes displaying a first region which includes information on an original document, and displaying a second region which includes information on virtual copy paper; changing the display of the second region in accordance with an input setting instruction; and when a copy instruction is input, copying the original document in accordance with the display of the second region. According to the present invention, an intuitive interface which even inexperienced users can easily use may be implemented.

Abstract translation: 提供了一种用于其的复印装置和用户界面方法。 所述用户界面方法包括显示包括关于原始文档的信息的第一区域，以及显示包括关于虚拟复印纸的信息的第二区域; 根据输入设置指令改变第二区域的显示; 并且当输入复制指令时，根据第二区域的显示复制原始文档。 根据本发明，可以实现即使没有经验的用户可以容易地使用的直观界面。

公开(公告)号：USD578132S1

公开(公告)日：2008-10-07

申请号：US29274286

申请日：2007-04-11

Applicant: Young Eun Lee

Designer： Young Eun Lee

公开(公告)号：US20050218395A1

公开(公告)日：2005-10-06

申请号：US11080737

申请日：2005-03-15

Applicant: Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

Inventor： Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

IPC: H01L21/20 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/78

Abstract: Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.

Abstract translation: 本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。 根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件 半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。 在本发明的实施例中可以去除第二组IV图案。 在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

公开(公告)号：US07998851B2

公开(公告)日：2011-08-16

申请号：US12715599

申请日：2010-03-02

Applicant: Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Sun-Ghil Lee ,  In-Soo Jung ,  Young-Eun Lee ,  Deok-Hyung Lee

Inventor： Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Sun-Ghil Lee ,  In-Soo Jung ,  Young-Eun Lee ,  Deok-Hyung Lee

IPC: H01L21/36

CPC classification number: H01L29/7842 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/0688

Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.

Abstract translation: 半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。 该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。 该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

公开(公告)号：US07429504B2

公开(公告)日：2008-09-30

申请号：US11080737

申请日：2005-03-15

Applicant: Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

Inventor： Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

IPC: H01L21/764 ,  H01L31/0336

CPC classification number: H01L29/0653 ,  H01L29/78

Abstract: Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.

Abstract translation: 本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。 根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件 半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。 在本发明的实施例中可以去除第二组IV图案。 在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

公开(公告)号：US07315063B2

公开(公告)日：2008-01-01

申请号：US11363176

申请日：2006-02-28

Applicant: Young-eun Lee ,  Seong-ghil Lee ,  Yu-gyun Shin ,  Jong-wook Lee ,  Young-pil Kim

Inventor： Young-eun Lee ,  Seong-ghil Lee ,  Yu-gyun Shin ,  Jong-wook Lee ,  Young-pil Kim

IPC: H01L29/76

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.

Abstract translation: 公开了一种CMOS晶体管结构及相关的制造方法，其中第一导电型MOS晶体管包括增强器，第二导电类型MOS晶体管包括由与增强器相同的材料形成的第二间隔物。 第二导电型MOS晶体管还包括相对于形成在凹陷区域中的外延层形成的源极/漏极区域。

公开(公告)号：US07204877B2

公开(公告)日：2007-04-17

申请号：US11104659

申请日：2005-04-13

Applicant: Young-Eun Lee ,  Mi-Young Han ,  Yeong-Rae Chang ,  Jeong-Jin Hong ,  Sung-Hoon Jang

Inventor： Young-Eun Lee ,  Mi-Young Han ,  Yeong-Rae Chang ,  Jeong-Jin Hong ,  Sung-Hoon Jang

IPC: C09D5/32 ,  C09D5/24

CPC classification number: C09D183/08 ,  C08G77/24 ,  C08K5/54 ,  C08L83/00 ,  C08L83/08 ,  C09D165/00 ,  G02B1/11 ,  G02B2207/109

Abstract: The present invention relates to a coating composition for forming an anti-reflective coating layer for a display device, comprising a fluorinated silane with low surface tension, a conductive polymer with antistatic properties, water, and a solvent. Thus, the coating film of the present invention prepared by coating the composition has high anti-reflection, excellent stain resistance to liquid-phase stains such as fingerprints and the solid-phase stains such as dust by controlling the refractive index, surface energy, and conductivity, and thus can be usefully applied to the outermost side of a display device, regardless of the type of substrates such as a Braun tube or a flat display film and the presence of other coating layers such as a hard coating layer and an anti-glare coating layer.

Abstract translation: 本发明涉及一种用于形成用于显示装置的抗反射涂层的涂料组合物，其包含具有低表面张力的氟化硅烷，具有抗静电性能的导电聚合物，水和溶剂。 因此，通过涂布组合物制备的本发明的涂膜通过控制折射率，表面能，以及表面能等而具有高的抗反射性，对指纹等的液相污渍以及灰尘等固相染料的耐污染性 导电性，并且因此可以有效地应用于显示装置的最外侧，而不管诸如布朗管或平面显示膜的基板的类型，以及其它涂层如硬涂层和抗反射层的存在， 眩光涂层。