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公开(公告)号：US20080186780A1
公开(公告)日：2008-08-07
申请号：US11703916
申请日：2007-02-07
IPC分类号： G11C16/14
CPC分类号： G11C11/5635 , G11C16/107 , G11C16/16 , G11C16/3459 , G11C2211/5621
摘要： A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a second region, wherein the second region is higher in threshold voltage than the fist region. The erasing operation implements a programming of memory bits that can inject negative charge carriers or electrons into a memory cell instead of using the conventional technique of injecting hot holes into the memory cell. This can avoid room temperature drift and charge loss caused by hot hole injection.
摘要翻译： 在具有多个存储单元的非易失性存储器中公开了一种用于执行擦除操作的方法。 至少一个存储器单元被编程为在编程之前具有第一区域中的阈值电压电平，并且在编程之后，存储器单元在第二区域中具有阈值电压电平，其中第二区域的阈值电压高于第一区域。 擦除操作实现了可以将负电荷载流子或电子注入到存储单元中的存储器位的编程，而不是使用将热空穴注入存储单元的常规技术。 这可以避免热空穴注入引起的室温漂移和电荷损失。
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公开(公告)号：US20080094891A1
公开(公告)日：2008-04-24
申请号：US11551974
申请日：2006-10-23
CPC分类号： G11C29/50 , G11C11/5642 , G11C16/04 , G11C29/50004 , G11C2211/5634 , G11C2211/5644
摘要： A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.
摘要翻译： 用于确定存储器阵列中的读取电压余量的方法将从存储器阵列读取的数据产生的读取和编码与从加载数据生成的预期总和进行比较。 读取电压（Vt）是步进的，将读取的和码与预期的和码进行比较，以确定提供匹配和码的Vt范围。 当Vt跨过其范围时，以并行方式确定多个读取电压余量（即，MLC存储器阵列的多个编程电平之间的读取电压余量）。
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公开(公告)号：US20070121386A1
公开(公告)日：2007-05-31
申请号：US11624612
申请日：2007-01-18
申请人： Wen Chiao Ho , Chin Chang , Kuen Chang , Chun Hung
发明人： Wen Chiao Ho , Chin Chang , Kuen Chang , Chun Hung
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5671 , G11C16/0475 , G11C16/3459
摘要： The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a first program level (level1) and a second program level (level2) to level 1, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a second program level (level2), and programming a first program level (level1).
摘要翻译： 本发明提供了一种在氮化物俘获存储器单元的多位单元中改变多电平单元编程的顺序的新颖方法，其减少或消除了程序步骤之间的电压阈值偏移，同时避免了在 读取窗口由互补位干扰引起。 在第一实施例中，本发明以具有四位的多位单元按以下顺序对多电平单元进行编程：编程第三程序电平（电平3），编程第一程序电平（电平1）和 第二程序级（级别2）到级别1，并且从第一程序级编程第二程序级。 在第二实施例中，本发明按照以下顺序对具有四位的多位单元中的多电平单元进行编程：编程第三程序电平（级别3），编程第二程序电平（级别2），以及 编程第一个程序级（1级）。
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公开(公告)号：US08347185B2
公开(公告)日：2013-01-01
申请号：US13456870
申请日：2012-04-26
CPC分类号： H03M13/13 , G06F11/1068 , H03M13/03 , H03M13/3776
摘要： A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.
摘要翻译： 用于检查存储器的读取错误的方法包括以下步骤。 接收到第一个数据片段。 产生根据第一数据片段的第一计数索引，其中第一计数索引对应于第一数据片段中的一种二进制值的数量。 第一个数据片段被写入存储器。 第一数据片段作为第二数据片段从存储器读取。 根据第二数据片段生成第二计数索引。 将第一计数指数与第二计数指数进行比较。
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公开(公告)号：US20120300562A1
公开(公告)日：2012-11-29
申请号：US13564189
申请日：2012-08-01
申请人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
发明人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
IPC分类号： G11C7/00
CPC分类号： G11C29/10 , G11C29/12005
摘要： A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.
摘要翻译： 提供了一种用于测试多芯片封装的方法和电路。 多芯片封装至少包括存储器芯片，并且存储器芯片包括多个存储器单元。 该方法包括对存储器单元执行正常读取操作，以检查从存储器单元读取的数据是否与存储器单元中的预置数据相同; 以及对所述存储器单元执行特殊读取操作，以检查从所述存储器单元读取的数据是否与期望值相同，其中所述期望值与存储在所述存储器单元中的数据无关。
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公开(公告)号：US07975111B2
公开(公告)日：2011-07-05
申请号：US12270722
申请日：2008-11-13
申请人： Chun-Hsiung Hung , Wen-Chiao Ho
发明人： Chun-Hsiung Hung , Wen-Chiao Ho
IPC分类号： G06F13/00
CPC分类号： G11C16/102
摘要： A memory and a method applied in one program command for the memory are provided. The memory includes a buffer and at least one program unit. The method includes the following steps. First, enter the program command to the memory. Next, enter user data to the buffer. Read the data of the program unit. Determine whether the user data fill the buffer. Fill the part of the buffer unoccupied by the user data with the data of the program unit if the user data do not fill the buffer. Erase the program unit if the program unit is not empty. Finally, program the data of the buffer into the program unit.
摘要翻译： 提供了在存储器的一个程序命令中应用的存储器和方法。 存储器包括缓冲器和至少一个程序单元。 该方法包括以下步骤。 首先，将程序命令输入到内存中。 接下来，输入用户数据到缓冲区。 读取程序单元的数据。 确定用户数据是否填充缓冲区。 如果用户数据没有填充缓冲区，则将用户数据中未占用的缓冲区的一部分填入程序单元的数据。 如果程序单元不为空，则擦除程序单元。 最后，将缓冲区的数据编程到程序单元中。
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公开(公告)号：US20110149675A1
公开(公告)日：2011-06-23
申请号：US12785297
申请日：2010-05-21
申请人： Chin-Hung Chang , Wen-Chiao Ho , Chun-Hsiung Hung
发明人： Chin-Hung Chang , Wen-Chiao Ho , Chun-Hsiung Hung
IPC分类号： G11C8/08
CPC分类号： G11C8/08
摘要： A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from multiple word line drivers.
摘要翻译： 公开了一种双晶体管字线驱动器。 所公开的公开的字线驱动器的示例通过p型和n型晶体管的栅极上的公共信号来简化。 所公开的字线驱动器的示例通过对从多个字线驱动器中选择的字线驱动器施加负电压而消耗较少的功率。
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公开(公告)号：US20110128786A1
公开(公告)日：2011-06-02
申请号：US12628710
申请日：2009-12-01
申请人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Shuo-Nan Hung , Chun-Hsiung Hung
CPC分类号： G11C16/16
摘要： A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines, wherein a first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.
摘要翻译： 存储器件包括存储器扇区，其包括存储器扇区，一行选择晶体管和多个驱动器。 存储器扇区包括多个字线，每个字线耦合到多个存储器单元。 选择晶体管行选择存储器扇区，并将存储器扇区与存储器件中紧邻的存储器扇区分开。 多个驱动器中的每一个耦合到多个字线中的一个，其中驱动器中的第一个耦合到字线中的第一个，以接收第一控制信号以传导第一字线和电压源 并且驱动器中的第二个耦合到第二个字线以接收第二控制信号以将第二字线与电压源断开。
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公开(公告)号：US07925960B2
公开(公告)日：2011-04-12
申请号：US11727256
申请日：2007-03-26
CPC分类号： H03M13/13 , G06F11/1068 , H03M13/03 , H03M13/3776
摘要： A method for checking reading errors of a memory includes receiving a first data fragment and accordingly generating a first ECC and a first count index; writing the first data fragment, the first ECC and the first count index into a memory; reading the first data fragment from the memory as a second data fragment, generating a second ECC and second count index according to the second data fragment; determining whether the first count index and second count index are equal; determining whether the first ECC and the second ECC are equal; and outputting the second data fragment when the first count index is equal to the second count index and the first ECC is equal to the second ECC.
摘要翻译： 用于检查存储器的读取错误的方法包括接收第一数据片段并相应地生成第一ECC和第一计数索引; 将第一数据片段，第一ECC和第一计数索引写入存储器; 从所述存储器读取所述第一数据片段作为第二数据片段，根据所述第二数据片段生成第二ECC和第二计数索引; 确定第一计数指数和第二计数指数是否相等; 确定第一ECC和第二ECC是否相等; 并且当所述第一计数索引等于所述第二计数索引并且所述第一ECC等于所述第二ECC时，输出所述第二数据片段。
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公开(公告)号：US07889572B2
公开(公告)日：2011-02-15
申请号：US12204009
申请日：2008-09-04
IPC分类号： G11C7/00
摘要： A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.
摘要翻译： 存储器包括多个存储区域，每个存储器区域包括目标存储器单元，源极线，位线和读取控制电路。 源极线耦合到目标存储器单元的第一端子。 位线耦合到目标存储器单元的第二端子。 读取控制电路用于选择性地向源极线施加工作电压。
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