公开(公告)号：US20090080243A1

公开(公告)日：2009-03-26

申请号：US12142724

申请日：2008-06-19

Applicant: Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Wen-Pin Lin

Inventor： Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C5/14 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078

Abstract: Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation mode. In the second operation mode, the invention generates a proper conduction period based on the resistance of the reference phase change storage element, and forces the write current into the controlled phase change storage element for the proper conduction period.

Abstract translation: 控制相变存储元件的装置和增加相变存储元件的可靠性的方法。 本发明引入了第一操作模式和第二操作模式。 参考相变存储元件在第一操作模式中强制写入电流以达到理想的导通时段。 在第二操作模式中，本发明基于参考相变存储元件的电阻产生适当的导通周期，并将写入电流强制到受控相变存储元件中以达到适当的导通周期。

公开(公告)号：US20090010047A1

公开(公告)日：2009-01-08

申请号：US11957044

申请日：2007-12-14

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

IPC: G11C11/56

CPC classification number: G11C13/0061 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source and outputs a driving current. The first switch device is controlled by a first control signal. The fast write control unit is coupled to the writing path to provide a writing voltage to the writing path. When the first switch device is turned off, the fast write control unit outputs the writing voltage to the writing path. When the first switch device is turned on, the fast write control unit stops outputting the writing voltage to the writing path.

Abstract translation: 提供了相变存储器写入电路。 该电路包括写入路径和快速写入控制单元。 写入路径还包括电流驱动单元，第一开关器件和相变存储器单元。 电流驱动单元耦合到高电压源并输出驱动电流。 第一开关装置由第一控制信号控制。 快速写入控制单元耦合到写入路径以向写入路径提供写入电压。 当第一开关装置关闭时，快速写入控制单元将写入电压输出到写入路径。 当第一开关装置接通时，快速写入控制单元停止向写入路径输出写入电压。

公开(公告)号：US20080157826A1

公开(公告)日：2008-07-03

申请号：US11739114

申请日：2007-04-24

Applicant: Ming-Daw Chen ,  Shyh-Shyuan Sheu ,  Wei-Chun Chang ,  Keng-Li Su

Inventor： Ming-Daw Chen ,  Shyh-Shyuan Sheu ,  Wei-Chun Chang ,  Keng-Li Su

IPC: H03K3/00

CPC classification number: G09G3/3648 ,  G09G2300/0465 ,  G09G2300/0809 ,  G09G2300/0823 ,  G09G2300/0857

Abstract: A voltage driving circuit, suitable for being used in a pixel driving circuit, includes a storage unit for receiving a single-end data input signal and outputting a first voltage signal and a second voltage signal according to a content of the data input signal. The first voltage signal and the second voltage signal have different voltage levels, and the voltage levels are a high voltage level and a low voltage level, which have been adjusted to a driving-voltage requirement satisfying subsequent operations. A switch control unit receives the first voltage signal and the second voltage signal and outputs an output-voltage signal at an output terminal based on a determination from at least one control signal. The output-voltage signal is the high voltage level or the low voltage level.

Abstract translation: 适用于像素驱动电路的电压驱动电路包括：存储单元，用于接收单端数据输入信号，并根据数据输入信号的内容输出第一电压信号和第二电压信号。 第一电压信号和第二电压信号具有不同的电压电平，并且电压电平是已经被调整到满足后续操作的驱动电压要求的高电压电平和低电压电平。 开关控制单元接收第一电压信号和第二电压信号，并且基于来自至少一个控制信号的确定在输出端输出输出电压信号。 输出电压信号为高电平或低电平。

公开(公告)号：US20070171732A1

公开(公告)日：2007-07-26

申请号：US11309037

申请日：2006-06-12

Applicant: Jan-Ruei Lin ,  Shyh-Shyuan Sheu ,  Wei-Jen Chang

Inventor： Jan-Ruei Lin ,  Shyh-Shyuan Sheu ,  Wei-Jen Chang

IPC: G11C7/10 ,  G11C11/00

CPC classification number: G11C13/0014 ,  B82Y10/00 ,  G11C2213/79

Abstract: An organic memory is provided. The organic memory at least comprises a plurality of select lines, a plurality of data lines, a bit cell array, and a plurality of digital sensing circuits. The bit cell array comprises a plurality of bit cells, wherein each bit cell comprises an organic memory cell and a switch element. Each digital sensing circuit comprises a current-to-voltage converter and a sensing block circuit. Therefore, the present invention provides a complete digital sensing mechanism of an organic memory IC, which is practicable and suitable for mass-production.

Abstract translation: 提供有机存储器。 有机存储器至少包括多条选择线，多条数据线，位单元阵列和多个数字感测电路。 位单元阵列包括多个位单元，其中每个位单元包括有机存储单元和开关元件。 每个数字感测电路包括电流 - 电压转换器和感测块电路。 因此，本发明提供了一种有机存储器IC的完整数字感测机构，其可行且适用于批量生产。

公开(公告)号：US07236390B1

公开(公告)日：2007-06-26

申请号：US11308146

申请日：2006-03-08

Applicant: Wei-Jen Chang ,  Shyh-Shyuan Sheu ,  Jan-Ruei Lin

Inventor： Wei-Jen Chang ,  Shyh-Shyuan Sheu ,  Jan-Ruei Lin

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/00 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0028 ,  G11C2213/79

Abstract: A bit cell of an organic memory is provided. The bit cell of the organic memory comprises an organic memory cell, a first transistor, a current mirror and a second transistor. To connect the organic memory cell to a data line, the first transistor is activated for reading and the second transistor is activated for writing. Furthermore, the first transistor has a greater size than the second transistor. Therefore, a fast processing time in writing and a large conduction current in reading are catered for. In addition, the current mirror amplifies the conduction current in reading and increases the capacity for resisting the interference by adjacent bit cell.

Abstract translation: 提供有机存储器的位单元。 有机存储器的位单元包括有机存储单元，第一晶体管，电流镜和第二晶体管。 为了将有机存储单元连接到数据线，第一晶体管被激活用于读取，第二晶体管被激活用于写入。 此外，第一晶体管具有比第二晶体管更大的尺寸。 因此，在写入时的快速处理时间和读取中的大的传导电流被满足。 此外，电流镜放大读取中的导通电流，并增加抵抗相邻位单元的干扰的能力。

公开(公告)号：US08218361B2

公开(公告)日：2012-07-10

申请号：US13215491

申请日：2011-08-23

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

Abstract translation: 提供了一种用于将写入数据存储到存储单元中的数据编程电路。 数据编程电路包括控制电路和电流产生电路。 控制电路根据写入数据生成控制信号。 电流产生电路向存储单元提供写入电流以改变存储单元的结晶状态。 写入电流具有对应于写入数据的脉冲宽度，并且结晶状态对应于写入数据。

公开(公告)号：US08040723B2

公开(公告)日：2011-10-18

申请号：US12650544

申请日：2009-12-31

Applicant: Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

Inventor： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC: G11C7/00

CPC classification number: G11C11/5678 ,  G11C7/14 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2211/5634

Abstract: A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

Abstract translation: 提供电压补偿电路，具有该电压补偿电路的多电平存储器件以及用于读取多电平存储器件的电压补偿方法。 当读取存储单元时，根据参考单元的漂移电阻的特性的变化来调整施加到存储器件的参考电压。 参考电压的增加值（即电压差）对应于由漂移条件引起的电阻变化。 漂移补偿机构适应于存储器件的读取驱动器的补偿电路，其可以补偿当从存储器单元读取数据时电压电平的变化。 当发生电阻漂移时，计算漂移量并将其加到参考电压上，以避免当读出存储的数据时由电阻漂移引起的判断误差。

公开(公告)号：US07796455B2

公开(公告)日：2010-09-14

申请号：US12142724

申请日：2008-06-19

Applicant: Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Wen-Pin Lin

Inventor： Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Wen-Pin Lin

IPC: G11C7/02

CPC classification number: G11C5/14 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078

Abstract: Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation mode. In the second operation mode, the invention generates a proper conduction period based on the resistance of the reference phase change storage element, and forces the write current into the controlled phase change storage element for the proper conduction period.

Abstract translation: 控制相变存储元件的装置和增加相变存储元件的可靠性的方法。 本发明引入了第一操作模式和第二操作模式。 参考相变存储元件在第一操作模式中强制写入电流以达到理想的导通时段。 在第二操作模式中，本发明基于参考相变存储元件的电阻产生适当的导通周期，并将写入电流强制到受控相变存储元件中以达到适当的导通周期。

公开(公告)号：US07796454B2

公开(公告)日：2010-09-14

申请号：US11967175

申请日：2007-12-29

Applicant: Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

Inventor： Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

IPC: G11C7/02

CPC classification number: G11C16/28 ,  G11C13/0004 ,  G11C13/004

Abstract: A sensing circuit of a phase change memory. The sensing circuit comprises a storage capacitor and a reference capacitor, a storage memory device and a reference memory device, a storage discharge switch and a reference discharge switch, and an arbitrator. First terminals of the storage capacitor and the reference capacitor are respectively coupled to a pre-charge voltage via first switches. First terminals of the storage memory device and the reference memory device are respectively coupled to the first terminals of the storage capacitor and the reference capacitor. The storage discharge switch and the reference discharge switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The arbitrator is coupled to the first terminals of the storage memory device and the reference memory device and provides an output as a read result of the storage memory device.

Abstract translation: 相变存储器的感测电路。 感测电路包括存储电容器和参考电容器，存储存储器件和参考存储器件，存储放电开关和参考放电开关以及仲裁器。 存储电容器和参考电容器的第一端子分别通过第一开关耦合到预充电电压。 存储存储器件和参考存储器件的第一端子分别耦合到存储电容器和参考电容器的第一端子。 存储放电开关和参考放电开关分别耦合到存储存储器件和参考存储器件的第二端子。 仲裁器耦合到存储存储器件和参考存储器件的第一端子，并提供输出作为存储存储器件的读取结果。

公开(公告)号：US07773411B2

公开(公告)日：2010-08-10

申请号：US12268581

申请日：2008-11-11

Applicant: Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/75 ,  G11C2213/76 ,  G11C2213/79

Abstract: A phase change memory wherein several phase change storage elements are coupled in series to share a single current source. The current provided by the current source is directed by a plurality of switches. To write/read the phase change storage elements, the invention provides techniques to control the current value generated by the current source and controls the states of the switches. The impedance summation of the phase change storage elements vary with the data stored therein.

Abstract translation: 一种相变存储器，其中几个相变存储元件串联耦合以共享单个电流源。 由电流源提供的电流由多个开关引导。 为了写入/读取相变存储元件，本发明提供了控制由当前源产生的当前值并控制开关状态的技术。 相变存储元件的阻抗求和随其中存储的数据而变化。