公开(公告)号：US07280415B2

公开(公告)日：2007-10-09

申请号：US11380749

申请日：2006-04-28

Applicant: Sang-Won Hwang ,  Dong-Kyu Youn

Inventor： Sang-Won Hwang ,  Dong-Kyu Youn

IPC: G11C7/00

CPC classification number: G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/76 ,  G11C29/82

Abstract: A memory device includes a nonvolatile memory cell array including a plurality of memory cells with a portion of the memory cells to store fuse data, and a fuse register to store the fuse data from the memory cell array. An operation of the memory device is modified in response to the fuse register.

Abstract translation: 一种存储器件包括：非易失性存储单元阵列，包括具有存储单元的一部分以存储熔丝数据的多个存储单元;以及熔丝寄存器，用于存储来自存储单元阵列的熔丝数据。 响应于熔丝寄存器修改存储器件的操作。

公开(公告)号：US20070183197A1

公开(公告)日：2007-08-09

申请号：US11655518

申请日：2007-01-19

Applicant: Min Gun Park ,  Kyong Ae Kim ,  Sang Won Hwang

Inventor： Min Gun Park ,  Kyong Ae Kim ,  Sang Won Hwang

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/0483 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: A non-volatile semiconductor memory device may include a memory cell array and a controller coupled to the memory cell array. The memory cell array may include first and second memory cells coupled to respective first and second word lines. Each of the first and second memory cells may be configured to be programmed to one of a first, a second, or a third threshold voltage so that the first and second memory cells provide nine different threshold voltage combinations. The controller may be configured to provide a mapping of data of a set of three binary bits providing eight different data combinations to eight of the nine different threshold voltage combinations provided by the first and second memory cells. The controller may be further configured to write data of first, second, and third binary bits to the first and second memory cells by programming each of the first and second memory cells to a respective one of the first, second, or third threshold voltages using the mapping of data. Related methods are also discussed.

Abstract translation: 非易失性半导体存储器件可以包括存储单元阵列和耦合到存储单元阵列的控制器。 存储单元阵列可以包括耦合到相应的第一和第二字线的第一和第二存储器单元。 第一和第二存储器单元中的每一个可以被配置为被编程为第一，第二或第三阈值电压中的一个，使得第一和第二存储器单元提供九个不同的阈值电压组合。 控制器可以被配置为提供一组三个二进制位的数据的映射，其提供八个不同数据组合到由第一和第二存储器单元提供的九个不同阈值电压组合中的八个。 控制器还可以被配置为通过将第一和第二存储器单元中的每一个编程为第一，第二或第三阈值电压中的相应的一个来将第一，第二和第三二进制位的数据写入第一和第二存储器单元，使用 数据的映射。 还讨论了相关方法。

公开(公告)号：US20070115724A1

公开(公告)日：2007-05-24

申请号：US11356417

申请日：2006-02-17

Applicant: Sang-Won Hwang

Inventor： Sang-Won Hwang

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/14

Abstract: A NAND flash memory device includes an array of NAND flash memory cells; a plurality of word lines connected to the NAND flash memory cells; and a plurality of bit lines connected to the NAND flash memory cells. Each bit line includes a first bit line portion, a second bit line portion, and a switching device extending between the first and second bit line portions to selectively connect the first and second bit line portions together. At least a first NAND flash memory cell is connected to the first bit line portion, and at least a second NAND flash memory cell is connected to the second bit line portion. By including primary and secondary page buffers, two pages of memory cells connected to a same group of bit lines can be programmed in a single programming operation, to achieve “double-speed” programming.

Abstract translation: NAND闪速存储器件包括NAND闪存单元的阵列; 连接到NAND闪存单元的多个字线; 以及连接到NAND闪存单元的多个位线。 每个位线包括第一位线部分，第二位线部分和在第一和第二位线部分之间延伸的选择性地将第一和第二位线部分连接在一起的开关器件。 至少第一NAND闪存单元连接到第一位线部分，并且至少第二NAND闪存单元连接到第二位线部分。 通过包括主页缓冲器和次页面缓冲器，可以在单个编程操作中编程连接到同一组位线的两页存储单元，以实现“双速”编程。

公开(公告)号：US20070058480A1

公开(公告)日：2007-03-15

申请号：US11511275

申请日：2006-08-29

Applicant: Sang-won Hwang

Inventor： Sang-won Hwang

IPC: G11C8/00

CPC classification number: G11C16/32 ,  G11C7/1027 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C16/0483

Abstract: A NAND flash memory device may include an interface block which receives an external read enable signal to output an internal clock signal during a read operation. The NAND flash memory device may also include a buffer clock controlling circuit which operates in response to a data output enable signal and the internal clock signal. The NAND flash memory device may also include a buffer clock generating circuit which receives the internal clock signal and which generates first and second buffer clock signals according to a control output of the buffer clock control circuit. The NAND flash memory device may also include a data output buffer circuit which sequentially outputs read data in response to one of the first and second buffer clock signals, wherein the buffer clock controlling circuit controls the buffer clock generating circuit to generate the second buffer clock signal having a single pulse when the data output enable signal is activated.

Abstract translation: NAND闪速存储器件可以包括在读取操作期间接收外部读使能信号以输出内部时钟信号的接口块。 NAND闪存器件还可以包括响应于数据输出使能信号和内部时钟信号而工作的缓冲器时钟控制电路。 NAND闪速存储器件还可以包括缓冲时钟发生电路，其接收内部时钟信号，并根据缓冲时钟控制电路的控制输出产生第一和第二缓冲时钟信号。 NAND闪存器件还可以包括响应于第一和第二缓冲时钟信号之一顺序地输出读取数据的数据输出缓冲器电路，其中缓冲时钟控制电路控制缓冲时钟产生电路以产生第二缓冲时钟信号 当数据输出使能信号被激活时具有单个脉冲。

公开(公告)号：US20070033449A1

公开(公告)日：2007-02-08

申请号：US11380749

申请日：2006-04-28

Applicant: Sang-Won HWANG ,  Dong-Kyu YOUN

Inventor： Sang-Won HWANG ,  Dong-Kyu YOUN

IPC: G11C29/00

CPC classification number: G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/76 ,  G11C29/82

Abstract: A memory device includes a nonvolatile memory cell array including a plurality of memory cells with a portion of the memory cells to store fuse data, and a fuse register to store the fuse data from the memory cell array. An operation of the memory device is modified in response to the fuse register.

Abstract translation: 一种存储器件包括：非易失性存储单元阵列，包括具有存储单元的一部分以存储熔丝数据的多个存储单元;以及熔丝寄存器，用于存储来自存储单元阵列的熔丝数据。 响应于熔丝寄存器修改存储器件的操作。

公开(公告)号：US20070025155A1

公开(公告)日：2007-02-01

申请号：US11354917

申请日：2006-02-16

Applicant: Sang-Won Hwang ,  Jin-Wook Lee

Inventor： Sang-Won Hwang ,  Jin-Wook Lee

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32

Abstract: A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a word line voltage generator configured to generate first and second sequences of voltage pulses. The device selectively supplies one of the first and second sequences of voltage pulses to a selected one of the word lines to program the nonvolatile memory cells connected to the selected word line. A slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses. In general, the first sequence is applied to word lines far away from the string select line (SSL), and the second sequence is applied to word lines that are close to the SSL.

Abstract translation: 非易失性存储器件包括非易失性存储单元阵列，包括连接到多个字线的多个非易失性存储器单元，字线电压发生器，被配置为产生第一和第二电压脉冲序列。 该装置选择性地将第一和第二电压脉冲序列中的一个提供给选定的字线之一，以编程连接到所选字线的非易失存储器单元。 电压脉冲的第一序列的至少一个电压脉冲的斜率大于第二电压脉冲序列的至少一个电压脉冲的斜率。 通常，第一个序列应用于远离字符串选择行（SSL）的字线，第二个序列应用于接近SSL的字线。

公开(公告)号：US20060279994A1

公开(公告)日：2006-12-14

申请号：US11264168

申请日：2005-11-02

Applicant: Min-Gun Park ,  Jin-Wook Lee ,  Sang-Won Hwang

Inventor： Min-Gun Park ,  Jin-Wook Lee ,  Sang-Won Hwang

IPC: G11C16/04

CPC classification number: G11C16/3404

Abstract: A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

公开(公告)号：US09343158B2

公开(公告)日：2016-05-17

申请号：US14165835

申请日：2014-01-28

Applicant: Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

Inventor： Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

IPC: G11C11/34 ,  G11C16/14 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459

Abstract: To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.

Abstract translation: 在非易失性存储器件中编程包括通过至少两个程序步骤被编程成多个状态的多个存储器单元，相对于耦合到所选择的存储单元，从擦除电平到第一目标电平执行主程序 字线相对于耦合到所选择的字线的存储器单元与原始程序相关联地从擦除电平执行预编程电平，其中预编程电平大于擦除电平并小于第一目标电平 相对于耦合到所选字线的预编程存储器单元，从预编程级到第二目标级执行次程序。

公开(公告)号：US07672162B2

公开(公告)日：2010-03-02

申请号：US12103176

申请日：2008-04-15

Applicant: Sang-won Hwang

Inventor： Sang-won Hwang

IPC: G11C16/04

CPC classification number: G11C16/3418

Abstract: A non-volatile memory device and system as well as a LSB read method are disclosed. The LSB read method includes reading LSB data from a memory cell during a main LSB read operation making reference to a flag cell threshold voltage, determining whether the LSB data contains an error, and if the LSB data contains an error re-reading the LSB data during a LSB recover-read operation without making reference to the flag cell threshold voltage.

Abstract translation: 公开了非易失性存储器件和系统以及LSB读取方法。 LSB读取方法包括在主LSB读取操作期间读取来自存储器单元的LSB数据，参考标志单元阈值电压，确定LSB数据是否包含错误，以及如果LSB数据包含重新读取LSB数据的错误 在LSB恢复读取操作期间，而不参考标志单元阈值电压。

公开(公告)号：US20100020618A1

公开(公告)日：2010-01-28

申请号：US12498477

申请日：2009-07-07

Applicant: Chan-Ho Kim ,  Sang-Won Hwang

Inventor： Chan-Ho Kim ,  Sang-Won Hwang

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C7/12 ,  G11C16/24

Abstract: A nonvolatile memory device includes a plurality of memory cells connected to a wordline and arranged in a row direction, bitlines connected to the plurality of memory cells, respectively, and a bitline bias circuit configured to separately control bias voltages provided to the bitlines according to positions of the memory cells along the row direction.

Abstract translation: 非易失性存储器件包括连接到字线并沿行方向布置的多个存储器单元，分别连接到多个存储器单元的位线和位线偏置电路，其被配置为根据位置分别控制提供给位线的偏置电压 的存储单元沿着行方向。