公开(公告)号：US06906349B2

公开(公告)日：2005-06-14

申请号：US10752510

申请日：2004-01-08

Applicant: Hyun-Jae Kim ,  Sook-Young Kang ,  Dong-Byum Kim ,  Su-Gyeong Lee ,  Myung-Koo Kang

Inventor： Hyun-Jae Kim ,  Sook-Young Kang ,  Dong-Byum Kim ,  Su-Gyeong Lee ,  Myung-Koo Kang

IPC: H01L51/50 ,  G09F9/30 ,  H01L21/00 ,  H01L21/20 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/12 ,  H01L27/32 ,  H01L29/04 ,  H01L29/786 ,  H01L29/788 ,  H01L31/036 ,  H01L31/0392 ,  H01L31/20 ,  H05B33/14

CPC classification number: H01L21/02678 ,  C30B13/24 ,  C30B29/06 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L27/1229 ,  H01L27/1285 ,  H01L27/1296 ,  Y10T428/24273

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.

公开(公告)号：US20050079693A1

公开(公告)日：2005-04-14

申请号：US10495673

申请日：2002-01-24

Applicant: Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang

Inventor： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang

IPC: G02F1/1368 ,  H01L21/20 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L21/02675 ,  H01L21/02532 ,  H01L21/0268 ,  H01L21/2026 ,  H01L29/66757 ,  H01L29/78675 ,  Y10S260/35

Abstract: A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line. The slit patterns arranged at the respective slit regions in the vertical direction are spaced from each other with a distance of 8*d. Alternatively, the first to fourth slit regions may be arranged in reverse order, or in the vertical direction.

Abstract translation: 用于形成多晶硅的掩模具有第一狭缝区域，其中垂直方向上布置多个水平狭缝图案，同时承载相同的宽度，在垂直方向上布置多个水平狭缝图案的第二狭缝区域，同时承载相同的宽度 宽度，在垂直方向上布置多个水平狭缝图案同时具有相同宽度的第三狭缝区域，以及沿垂直方向布置多个水平狭缝图案的第四狭缝区域，同时承载相同的宽度。 布置在第一至第四狭缝区域的狭缝图案在第一狭缝区域上与狭缝图案的宽度d成一定比例地沿水平方向的宽度依次增大。 沿水平方向布置在第一至第四狭缝区域处的狭缝图案的中心位于相同的线上。 在垂直方向的各个狭缝区域上排列的狭缝图案彼此间隔8 * d。 或者，第一至第四狭缝区域可以以相反的顺序或在垂直方向上布置。

公开(公告)号：US20110222015A1

公开(公告)日：2011-09-15

申请号：US13005224

申请日：2011-01-12

Applicant: Myung-Koo KANG

Inventor： Myung-Koo KANG

IPC: G02F1/1339

CPC classification number: G02F1/1339 ,  G02F1/133784

Abstract: A liquid crystal display including: a first substrate on which a first electrode and a first orientation layer are formed; a second substrate facing the first substrate and including a second electrode and a second orientation layer; a sealant formed along edges of the first substrate and the second substrate; and a liquid crystal layer between the first electrode and the second electrode; wherein holes are formed in the first and second orientation layers and the sealant is bonded to the first and second subatrates through both side holes. Since a contact area between the sealant and the substrates is increased and a bonding force is improved, a stable sealing state can be maintained with a small area and a size of a non-pixel region is reduced so that a small-sized liquid crystal display can be achieved.

Abstract translation: 一种液晶显示器，包括：形成有第一电极和第一取向层的第一基板; 面向所述第一基板的第二基板，并且包括第二电极和第二取向层; 沿着所述第一基板和所述第二基板的边缘形成的密封剂; 以及在所述第一电极和所述第二电极之间的液晶层; 其中在第一和第二取向层中形成孔，并且密封剂通过两个侧孔结合到第一和第二下层。 由于密封剂和基板之间的接触面积增加，粘合力提高，所以能够以小的面积保持稳定的密封状态，并且减小非像素区域的尺寸，使得小型液晶显示器 可以实现。

公开(公告)号：US20080206912A1

公开(公告)日：2008-08-28

申请号：US12110678

申请日：2008-04-28

Applicant: Soong-Yong JOO ,  Myung-Koo KANG

Inventor： Soong-Yong JOO ,  Myung-Koo KANG

IPC: H01L21/20 ,  H01L21/00

CPC classification number: H01L27/1285 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/0268 ,  H01L21/02691 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757

Abstract: An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one block that are extended in a plurality of directions. The pixel electrode is electrically connected to the switching element. Therefore, current mobility and design margin of the switching element are improved.

Abstract translation: 阵列基板包括基底基板，开关元件和像素电极。 开关元件在基底基板上。 开关元件包括具有至少一个块的多晶硅图案。 在沿多个方向延伸的至少一个块中的每一个中形成谷粒。 像素电极电连接到开关元件。 因此，提高了开关元件的电流移动性和设计余量。

公开(公告)号：US07294538B2

公开(公告)日：2007-11-13

申请号：US10532459

申请日：2003-10-21

Applicant: Hyun-Jae Kim ,  Myung-Koo Kang

Inventor： Hyun-Jae Kim ,  Myung-Koo Kang

IPC: H01L21/84

CPC classification number: H01L27/1285 ,  B23K26/02 ,  B23K26/066 ,  H01L21/02532 ,  H01L21/0268 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78675

Abstract: A device for irradiating a laser beam onto an amorphous silicon thin film formed on a substrate. The device includes: a stage mounting the substrate; a laser oscillator for generating a laser beam; a projection lens for focusing and guiding the laser beam onto the thin film; a reflector for reflecting the laser beam guided onto the thin film; a controller for controlling a position of the reflector, and an absorber for absorbing the laser beam reflected by the reflector.

Abstract translation: 用于将激光束照射到形成在基板上的非晶硅薄膜上的装置。 该装置包括：安装基板的台架; 用于产生激光束的激光振荡器; 用于将激光束聚焦并引导到薄膜上的投影透镜; 用于反射引导到薄膜上的激光束的反射器; 用于控制反射器的位置的控制器和用于吸收由反射器反射的激光束的吸收体。

公开(公告)号：US07229860B2

公开(公告)日：2007-06-12

申请号：US10499090

申请日：2002-01-29

Applicant: Jean-Ho Song ,  Joon-Hoo Choi ,  Beom-Rak Choi ,  Myung-Koo Kang ,  Sook-Young Kang

Inventor： Jean-Ho Song ,  Joon-Hoo Choi ,  Beom-Rak Choi ,  Myung-Koo Kang ,  Sook-Young Kang

IPC: H01L21/00

CPC classification number: H01L29/66757 ,  H01L29/78675

Abstract: A manufacturing method of a thin film transistor. An amorphous silicon thin film is formed on an insulating substrate, and is crystallized by a lateral solidification process with illumination of laser beams into the amorphous silicon thin film to form a polysilicon thin film. Next, protrusion portions protruding from the surface of the polysilicon thin film are removed by plasma dry-etching using a gas mixture including Cl2, SF6 and Ar at the ratio of 3:1:2 to smooth the surface of the polysilicon thin film, and the semiconductor layer is formed by patterning the polysilicon thin film. A gate insulating film covering the semiconductor layer is formed and a gate electrode is formed on the gate insulating film opposite the semiconductor layer. A source region and a drain region opposite each other with respect to the gate electrode are formed by implanting impurities into the semiconductor layer and a source electrode and drain electrode are formed to be electrically connected to the source region and drain region.

Abstract translation: 薄膜晶体管的制造方法。 在绝缘基板上形成非晶硅薄膜，并通过横向固化工艺使激光束照射到非晶硅薄膜中而形成多晶硅薄膜而结晶。 接下来，通过使用包含Cl 2，SF 6和Ar的气体混合物的等离子体干蚀刻来除去从多晶硅薄膜的表面突出的突出部分， 3：1：2以平滑多晶硅薄膜的表面，并且通过图案化多晶硅薄膜形成半导体层。 形成覆盖半导体层的栅极绝缘膜，并且在与半导体层相对的栅极绝缘膜上形成栅电极。 通过将杂质注入到半导体层中而形成源极区和相对于栅极彼此相对的漏极区，源电极和漏电极形成为与源区和漏区电连接。

公开(公告)号：US07217642B2

公开(公告)日：2007-05-15

申请号：US10495673

申请日：2002-01-24

Applicant: Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang

Inventor： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang

IPC: H01L21/20

CPC classification number: H01L21/02675 ,  H01L21/02532 ,  H01L21/0268 ,  H01L21/2026 ,  H01L29/66757 ,  H01L29/78675 ,  Y10S260/35

Abstract: A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line. The slit patterns arranged at the respective slit regions in the vertical direction are spaced from each other with a distance of 8*d. Alternatively, the first to fourth slit regions may be arranged in reverse order, or in the vertical direction.

Abstract translation: 用于形成多晶硅的掩模具有第一狭缝区域，其中垂直方向上布置多个水平狭缝图案，同时承载相同的宽度，在垂直方向上布置多个水平狭缝图案的第二狭缝区域，同时承载相同的宽度 宽度，在垂直方向上布置多个水平狭缝图案同时具有相同宽度的第三狭缝区域，以及沿垂直方向布置多个水平狭缝图案的第四狭缝区域，同时承载相同的宽度。 布置在第一至第四狭缝区域的狭缝图案在第一狭缝区域上与狭缝图案的宽度d成一定比例地沿水平方向的宽度依次增大。 沿水平方向布置在第一至第四狭缝区域处的狭缝图案的中心位于相同的线上。 在垂直方向的各个狭缝区域上排列的狭缝图案彼此间隔8 * d。 或者，第一至第四狭缝区域可以以相反的顺序或在垂直方向上布置。

公开(公告)号：US07183574B2

公开(公告)日：2007-02-27

申请号：US10500514

申请日：2003-01-03

Applicant: Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang ,  Woo-Suk Chung

Inventor： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang ,  Woo-Suk Chung

IPC: H01L21/00

CPC classification number: H01L29/42384 ,  G02F1/13454 ,  G02F2202/104 ,  H01L21/02675 ,  H01L21/2026 ,  H01L29/78675

Abstract: The present invention relates to a thin film transistor and a liquid crystal display. A gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of the driving circuit. A thin film transistor according to the present invention includes a semiconductor pattern a thin film of poly-crystalline silicon containing grown grains on the insulating substrate. The semiconductor pattern includes a channel region and source and drain regions opposite with respect to the channel region. A gate insulating layer covers the semiconductor pattern. On the gate insulating layer, a gate electrode including at least one portion extending in a direction crossing the growing direction of the grains and overlapping the channel region is formed. In a liquid crystal display according to the present invention, a plurality of thin film transistors forming a data driver circuit include thin films of polycrystalline silicon formed by sequential lateral solidification, at least one portion of a gate electrode of each thin film transistor extends in a direction crossing the grain growing direction, and at least one of the plurality of thin film transistors has a gate electrode having a pattern different from other thin film transistors.

Abstract translation: 本发明涉及薄膜晶体管和液晶显示器。 栅电极被形成为包括沿垂直于增益生长方向的方向延伸的至少一个部分，以使TFT的电荷迁移率均匀，而不增加驱动电路的尺寸。 根据本发明的薄膜晶体管包括在绝缘基板上具有含有生长晶粒的多晶硅薄膜的半导体图案。 半导体图案包括沟道区和相对于沟道区相反的源极和漏极区。 栅极绝缘层覆盖半导体图案。 在栅极绝缘层上形成栅电极，该栅电极具有沿与晶粒的生长方向交叉的方向延伸的至少一部分，与沟道区重叠。 在根据本发明的液晶显示器中，形成数据驱动电路的多个薄膜晶体管包括通过顺序横向固化形成的多晶硅薄膜，每个薄膜晶体管的栅电极的至少一部分以 方向与晶粒生长方向交叉，并且多个薄膜晶体管中的至少一个具有与其它薄膜晶体管不同的图案的栅电极。

公开(公告)号：US20070026549A1

公开(公告)日：2007-02-01

申请号：US11386630

申请日：2006-03-22

Applicant: Soong-Yong Joo ,  Myung-Koo Kang

Inventor： Soong-Yong Joo ,  Myung-Koo Kang

IPC: H01L21/00

CPC classification number: H01L27/1285 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/0268 ,  H01L21/02691 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757

Abstract: An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one block that are extended in a plurality of directions. The pixel electrode is electrically connected to the switching element. Therefore, current mobility and design margin of the switching element are improved.

Abstract translation: 阵列基板包括基底基板，开关元件和像素电极。 开关元件在基底基板上。 开关元件包括具有至少一个块的多晶硅图案。 在沿多个方向延伸的至少一个块中的每一个中形成谷粒。 像素电极电连接到开关元件。 因此，提高了开关元件的电流移动性和设计余量。

公开(公告)号：US07892704B2

公开(公告)日：2011-02-22

申请号：US11653667

申请日：2007-01-12

Applicant: Myung Koo Kang ,  Soong Yong Joo

Inventor： Myung Koo Kang ,  Soong Yong Joo

IPC: G01F9/00 ,  C30B28/08

CPC classification number: H01L21/0268 ,  H01L21/02532 ,  H01L21/02691 ,  H01L27/1285

Abstract: A mask for silicon crystallization capable of minimizing the number of grain boundaries in crystallized silicon, a method for crystallizing silicon using the mask, and a display device are presented. The mask includes a group of slits that are inclined at a predetermined angle with respect to a scan direction and a group of slits including slits inclined at a predetermined angle with respect to the former group of slits. The groups of slits are separated by an interval along the scan direction, and the substrate and/or mask is moved by the interval between irradiation by laser through the slits. Further, there are provided a method for crystallizing silicon using the mask and a display device. By reducing the number of grain boundaries that extend horizontally or vertically on the substrate, the invention obviates a design limitation associated with the directional anisotropy in sequential lateral solidification (SLS) technique.

Abstract translation: 提出了能够使结晶硅中的晶界数最小化的硅结晶掩模，使用该掩模的硅结晶方法和显示装置。 掩模包括相对于扫描方向以预定角度倾斜的一组狭缝和包括相对于前一组狭缝以预定角度倾斜的狭缝的一组狭缝。 这些狭缝组沿着扫描方向分开一段间隔，并且衬底和/或掩模以激光通过狭缝照射之间的间隔移动。 此外，提供了使用掩模和显示装置使硅结晶的方法。 通过减少在衬底上水平或垂直延伸的晶界的数量，本发明避免了在顺序横向固化（SLS）技术中与方向各向异性相关的设计限制。