LDPC DECODER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF

    公开(公告)号:US20200218607A1

    公开(公告)日:2020-07-09

    申请号:US16691278

    申请日:2019-11-21

    Abstract: A semiconductor memory system including: a semiconductor memory device suitable for storing a codeword; and an LDPC decoder suitable for decoding the codeword to generate decoded data, wherein the LDPC decoder includes: a message passing decoding component suitable for performing a first decoding operation of decoding the codeword, and calculating the minimum value among numbers of UCNs; and an error path detection component suitable for detecting error path candidates using a tree in which each of UCNs corresponding to the minimum value is set to a root node, sorting the detected error path candidates in ascending order of maximum LLRs, resetting symbol values and LLRs of variable nodes in the error path candidates, and providing the message passing decoding unit with information on the reset symbol values and LLRs.

    REFERENCE VOLTAGE GENERATING CIRCUIT
    388.
    发明申请

    公开(公告)号:US20200209906A1

    公开(公告)日:2020-07-02

    申请号:US16543314

    申请日:2019-08-16

    Abstract: A reference voltage generating circuit includes a bandgap reference (BGR) circuit configured to output an active reference voltage at a first node according to a sample signal; a first charging circuit configured to charge a first capacitor using the active reference voltage according to the sample signal; a second charging circuit configured to charge a second capacitor using the active reference voltage according to the sample signal; and a comparing circuit configured to compare a voltage difference between a charge voltage of the first capacitor and a charge voltage of the second capacitor with a threshold value, wherein the sample signal is a pulse signal generated using an output of the comparing circuit and the charge voltage of the first capacitor is provided as a low power reference voltage in a low power operation mode.

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