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    Vertical DRAM structure and method
    311.
    发明授权
    Vertical DRAM structure and method 有权

    公开(公告)号：US12302553B2

    公开(公告)日：2025-05-13

    申请号：US17668770

    申请日：2022-02-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Ta Yu ,  Bo-Feng Young ,  Hung Wei Li ,  Sai-Hooi Yeong ,  Chi On Chui

    IPC: H10B12/00 ,  H01L29/10

    Abstract: Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.

    SYSTEM-ON-CHIP WITH FERROELECTRIC RANDOM ACCESS MEMORY AND TUNABLE CAPACITOR
    312.
    发明申请
    SYSTEM-ON-CHIP WITH FERROELECTRIC RANDOM ACCESS MEMORY AND TUNABLE CAPACITOR 有权

    公开(公告)号：US20250151285A1

    公开(公告)日：2025-05-08

    申请号：US19013848

    申请日：2025-01-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sai-Hooi Yeong ,  Chi On Chui ,  Chenchen Jacob Wang

    IPC: H10B53/40 ,  H10B53/30 ,  H10D1/68

    Abstract: A semiconductor device includes: a substrate; a first dielectric layer over the substrate; a memory cell over the substrate in a first region of the semiconductor device, where the memory cell includes a first ferroelectric structure in the first dielectric layer, where the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer in between; and a tunable capacitor over the substrate in a second region of the semiconductor device, where the tunable capacitor includes a second ferroelectric structure, where the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer in between, where at least a portion of the second ferroelectric structure is in the first dielectric layer.

    Photoresist and Method
    317.
    发明申请
    Photoresist and Method 有权

    公开(公告)号：US20250102916A1

    公开(公告)日：2025-03-27

    申请号：US18973300

    申请日：2024-12-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Liang-Yi Chang ,  Tai-Chun Huang ,  Chi On Chui

    IPC: G03F7/09 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311

    Abstract: Multi-layer photoresists, methods of forming the same, and methods of patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a reflective film stack over a target layer, the reflective film stack including alternating layers of a first material and a second material, the first material having a higher refractive index than the second material; depositing a photosensitive layer over the reflective film stack; patterning the photosensitive layer to form a first opening exposing the reflective film stack, patterning the photosensitive layer including exposing the photosensitive layer to a patterned energy source, the reflective film stack reflecting at least a portion of the patterned energy source to a backside of the photosensitive layer; patterning the reflective film stack through the first opening to form a second opening exposing the target layer; and patterning the target layer through the second opening.

    Semiconductor device with isolation structure
    318.
    发明授权
    Semiconductor device with isolation structure 有权

    公开(公告)号：US12255205B2

    公开(公告)日：2025-03-18

    申请号：US17826845

    申请日：2022-05-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chieh-Ping Wang ,  Tai-Chun Huang ,  Yung-Cheng Lu ,  Ting-Gang Chen ,  Chi On Chui

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H10B99/00

    Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.

    Semiconductor device and methods of forming the same
    320.
    发明授权
    Semiconductor device and methods of forming the same 有权

    公开(公告)号：US12243786B2

    公开(公告)日：2025-03-04

    申请号：US17744334

    申请日：2022-05-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-I Lin ,  Da-Yuan Lee ,  Chi On Chui

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: An embodiment includes a device including a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a hybrid fin over the substrate, the hybrid fin disposed between the first semiconductor fin and the second semiconductor fin, and the hybrid fin having an oxide inner portion extending downward from a top surface of the hybrid fin. The device also includes a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, the hybrid fin extending above a top surface of the first isolation region, a high-k gate dielectric over sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin, a gate electrode on the high-k gate dielectric, and source/drain regions on the first semiconductor fin on opposing sides of the gate electrode.

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