公开(公告)号：US20240028779A1

公开(公告)日：2024-01-25

申请号：US18376928

申请日：2023-10-05

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Gregory Allen NORTH ,  Per Torstein ROINE ,  Eric Thierry Jean PEETERS

IPC分类号： G06F21/85 ,  G06F13/28

CPC分类号： G06F21/85 ,  G06F13/287 ,  G06F15/7807

摘要： A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit has a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

公开(公告)号：US20240028738A1

公开(公告)日：2024-01-25

申请号：US18026582

申请日：2021-09-09

申请人： ALIBABA GROUP HOLDING LIMITED

发明人： Hui Wang ,  Zhichao Li ,  Jicheng Chen ,  Zilong Huang ,  Tao Lyu ,  Fang Liu ,  Zhiqian Wang

IPC分类号： G06F21/57 ,  G06F21/85

CPC分类号： G06F21/575 ,  G06F21/572 ,  G06F21/85

摘要： Embodiments of the present application provide a trusted authentication system, method, mainboard, micro board, and a storage medium. According to the solution provided by the embodiments of the present application, when the system is powered on and starts, trusted authentication of a micro board itself is performed on the basis of a first trusted platform control module TPCM on the micro board and, after the authentication is passed, the other components in the micro board are controlled to leave a reset state and trusted authentication of the mainboard is performed by means of a mainboard authentication component used for performing trusted authentication of the mainboard.

公开(公告)号：US11876732B2

公开(公告)日：2024-01-16

申请号：US17100505

申请日：2020-11-20

申请人： STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

发明人： Daniel Olson ,  Loic Pallardy ,  Nicolas Anquet

IPC分类号： H04L41/0803 ,  H04L49/109 ,  G06F21/85

CPC分类号： H04L49/109 ,  G06F21/85 ,  H04L41/0803

摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.

公开(公告)号：US11856101B2

公开(公告)日：2023-12-26

申请号：US18068906

申请日：2022-12-20

申请人： KAZUAR ADVANCED TECHNOLOGIES LTD.

发明人： Daniel Mondy Finchelstein ,  Yuval Moshe Porat ,  Shlomi Raz Marco

IPC分类号： H04L9/32 ,  G06F21/60 ,  H04L9/08 ,  G06F21/82 ,  G06F21/83 ,  G06F21/84 ,  G06F21/85 ,  H04L12/06 ,  H04L12/50

CPC分类号： H04L9/32 ,  G06F21/606 ,  H04L9/088

摘要： A method for providing a secured client computer that includes peripheral components. Each peripheral component processes a corresponding peripheral component data of a data type that is not compatible with peripheral component data types processed by a processor of other peripheral components. The processor of each peripheral component codes the corresponding data of the data type for establishing a secured peer-to-peer communication with other peripheral components.

公开(公告)号：US11853426B2

公开(公告)日：2023-12-26

申请号：US17660420

申请日：2022-04-25

申请人： Vladimir Mickael Leal Monteiro

发明人： Vladimir Mickael Leal Monteiro

IPC分类号： H04L29/06 ,  G06F21/56 ,  G06F21/32 ,  H04L9/40 ,  G06F21/82 ,  G06F21/55 ,  H04W12/128 ,  G06F16/27 ,  G06F16/182 ,  H04L9/08 ,  H04L9/32 ,  H04L41/0806 ,  H04L41/00 ,  H04L61/4511 ,  G06F21/81 ,  G06F21/85 ,  G06F21/86 ,  H04L9/00

CPC分类号： G06F21/567 ,  G06F16/182 ,  G06F16/27 ,  G06F21/32 ,  G06F21/55 ,  G06F21/81 ,  G06F21/82 ,  G06F21/85 ,  G06F21/86 ,  H04L9/0838 ,  H04L9/3226 ,  H04L9/3239 ,  H04L9/3247 ,  H04L41/0806 ,  H04L41/24 ,  H04L61/4511 ,  H04L63/0227 ,  H04L63/0236 ,  H04L63/0861 ,  H04L63/107 ,  H04L63/20 ,  H04W12/128 ,  H04L9/50 ,  H04L2209/80

摘要： The portable peripheral (100) of communication with the data network (105) utilizing the internet protocol, comprises:



a connector (110) to mechanically connect and establish a removable wired connection between the peripheral and a portable terminal,
a first means (115) of wired bidirectional communication with the portable terminal,
a second means (120) of bidirectional communication with a data network and
a unit security (122) protecting the communication between the first and the second means of communication, this communication being established between the first and the second means of communication, the security unit (122) comprising a system (127) of autonomous DNS management,
the means of communication and the security unit being embedded in a unique housing (130) removable from the portable terminal.

公开(公告)号：US11847254B2

公开(公告)日：2023-12-19

申请号：US17581094

申请日：2022-01-21

申请人： Shift5, Inc.

发明人： Phillip T. Weigand ,  Matthew J. Rogers ,  Olivia I. Puleo ,  Joshua A. Lospinoso ,  Michael A. Weigand

IPC分类号： G06F21/85 ,  G06F21/81

CPC分类号： G06F21/85 ,  G06F21/81

摘要： An apparatus for preventing physical intrusion on a data bus includes a data bus state sensor coupled to the data bus for monitoring a state of the data bus, a power circuit for generating multiple voltages supplied to functional circuitry in the apparatus, and a variable override circuit. The variable override circuit receives one or more voltages from the power circuit and selectively gates the voltages onto the data bus as a function of one or more control signals. A controller coupled to the variable override circuit, the power circuit and the state sensor receives state information from the state sensor and generates the control signals in response to detection of physical intrusion on the data bus. The controller controls a voltage level of at least one of the voltages generated by the power circuit for overriding the data bus when physical intrusion is detected on the data bus.

公开(公告)号：US11847211B2

公开(公告)日：2023-12-19

申请号：US17742865

申请日：2022-05-12

申请人： Intel Corporation

发明人： Marcio Juliato ,  Manoj Sastry ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Qian Wang ,  Vuk Lesi

IPC分类号： G06F21/55 ,  G06F21/71 ,  G06F21/85

CPC分类号： G06F21/554 ,  G06F21/71 ,  G06F21/85 ,  G06F2221/034

摘要： A platform comprising numerous reconfigurable circuit components arranged to operate as primary and redundant circuits is provided. The platform further comprises security circuitry arranged to monitor the primary circuit for anomalies and reconfigurable circuit arranged to disconnect the primary circuit from a bus responsive to detection of an anomaly. Furthermore, the present disclosure provides for the quarantine, refurbishment and designation as redundant, the anomalous circuit.

公开(公告)号：US11829304B2

公开(公告)日：2023-11-28

申请号：US15851399

申请日：2017-12-21

申请人： McAfee, LLC

发明人： Cedric Cochin ,  Jonathan Edwards ,  Aditya Kapoor

IPC分类号： G06F13/12 ,  H04W12/04 ,  G06F9/44 ,  G06F21/44 ,  G06F21/35 ,  G06F13/38 ,  G06F9/4401 ,  G06F21/56 ,  G06F21/85 ,  H04W12/06 ,  H04W12/50 ,  G06F21/53 ,  H04W12/61 ,  H04W12/68

CPC分类号： G06F13/126 ,  G06F9/4411 ,  G06F13/385 ,  G06F21/35 ,  G06F21/44 ,  G06F21/445 ,  G06F21/566 ,  G06F21/85 ,  H04W12/04 ,  H04W12/06 ,  H04W12/50 ,  G06F21/53 ,  H04W12/61 ,  H04W12/68

摘要： Pairing of an external device using a random user action is disclosed herein. An example method includes restricting the external device from accessing a resource. A user input receivable from the external device is identified based on a type of the external device, the user input not included in a list of previously generated user actions. In response to receipt of the user input from the external device within a threshold time period, the external device is authorized to access the resource.

公开(公告)号：US20230376637A1

公开(公告)日：2023-11-23

申请号：US18363176

申请日：2023-08-01

申请人： Intel Corporation

发明人： Manoj R. Sastry ,  Alpa Narendra Trivedi ,  Men Long

IPC分类号： G06F21/72 ,  G09C1/00 ,  G06F21/85 ,  H04L9/06 ,  H04L9/08

CPC分类号： G06F21/72 ,  G09C1/00 ,  G06F21/85 ,  H04L9/0643 ,  H04L9/0897 ,  H04L2209/76 ,  G06F2213/0038 ,  G06F2207/7219 ,  G06F2211/008

摘要： Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.

公开(公告)号：US11816253B2

公开(公告)日：2023-11-14

申请号：US17130506

申请日：2020-12-22

申请人： Intel Corporation

发明人： Alpa Trivedi ,  Steffen Schulz ,  Patrick Koeberl

IPC分类号： G06F21/85 ,  G06F30/398 ,  G06N3/04 ,  H04L9/08 ,  G06F9/30 ,  G06F9/50 ,  G06F15/177 ,  G06F15/78 ,  H04L9/40 ,  G06F11/07 ,  G06F30/331 ,  G06F9/38 ,  G06F11/30 ,  G06F119/12 ,  G06F21/76 ,  G06N3/08 ,  H04L9/00 ,  G06F111/04 ,  G06F30/31 ,  G06F21/30 ,  G06F21/53 ,  G06F21/57 ,  G06F21/73 ,  G06F21/74 ,  G06N20/00 ,  G06F21/71 ,  G06F21/44

CPC分类号： G06F21/85 ,  G06F9/30101 ,  G06F9/3877 ,  G06F9/505 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/0754 ,  G06F11/0793 ,  G06F11/3058 ,  G06F15/177 ,  G06F15/7825 ,  G06F15/7867 ,  G06F30/331 ,  G06F30/398 ,  G06N3/04 ,  H04L9/0877 ,  H04L63/0442 ,  H04L63/12 ,  H04L63/20 ,  G06F11/0772 ,  G06F11/3051 ,  G06F21/30 ,  G06F21/44 ,  G06F21/53 ,  G06F21/57 ,  G06F21/575 ,  G06F21/71 ,  G06F21/73 ,  G06F21/74 ,  G06F21/76 ,  G06F30/31 ,  G06F2111/04 ,  G06F2119/12 ,  G06F2221/034 ,  G06N3/08 ,  G06N20/00 ,  H04L9/008 ,  H04L9/0841

摘要： An apparatus to facilitate enabling secure communication via attestation of multi-tenant configuration on accelerator devices is disclosed. The apparatus includes a processor to: verify a base bitstream of an accelerator device, the base bitstream published by a cloud service provider (CSP); verify partial reconfiguration (PR) boundary setups and PR isolation of an accelerator device, the PR boundary setups and PR isolation published by the CSP; generate PR bitstream to fit within at least one PR region of the PR boundary setups of the accelerator device; inspect accelerator device attestation received from a secure device manager (SDM) of the accelerator device; and responsive to successful inspection of the accelerator device attestation, provide the PR bitstream to the CSP for PR reconfiguration of the accelerator device.