公开(公告)号：US09106504B1

公开(公告)日：2015-08-11

申请号：US14055063

申请日：2013-10-16

申请人： Altera Corporation

发明人： Chiang Wei Lee ,  Han Hua Leong ,  Keen Yew Loke ,  Siew Leong Lam

IPC分类号： H04L5/16 ,  H04L25/40

CPC分类号： H04L25/14

摘要： Transceiver circuitry may include a storage element that receives data signals from an external element, an alignment detector circuit, and a register. The storage element has a write clock terminal that receives a channel clock signal and a read clock terminal that receives another channel clock signal. The alignment detector circuit is adapted to generate an asserted ready signal when a predefined pattern is detected in the received data signals. The register receives an output signal from the storage element and outputs the output signal based on the asserted ready signal that is generated by the alignment detector circuit. The register may be clocked by the same channel clock signal that is received at the read clock terminal of the storage element.

摘要翻译： 收发器电路可以包括从外部元件接收数据信号的存储元件，对准检测器电路和寄存器。 存储元件具有接收通道时钟信号的写时钟端子和接收另一通道时钟信号的读时钟端子。 当在所接收的数据信号中检测到预定模式时，对准检测器电路适于产生断言​​的就绪信号。 该寄存器接收来自存储元件的输出信号，并且基于由对准检测器电路产生的被断言就绪信号输出输出信号。 寄存器可以由在存储元件的读取时钟端接收的相同通道时钟信号来计时。

公开(公告)号：US08929499B2

公开(公告)日：2015-01-06

申请号：US13631874

申请日：2012-09-29

申请人： Intel Corporation

发明人： Fangxing Wei ,  Subratakumar Mandal

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40 ,  H04B1/16

CPC分类号： H04L7/0087 ,  H04B1/16 ,  H04L1/205 ,  H04L7/0016 ,  H04L7/0025 ,  H04L7/10

摘要： Methods and apparatus for improving system timing margin of high speed I/O (input/output) interconnect links by using fine training of a phase interpolator are described. In some embodiments, I/O links use forward clock architecture to send data from transmit driver to receiver logic. Moreover, at the receiver side, Phase Interpolator (PI) logic may be used to place the sampling clock at the center of the valid data window or eye. In an embodiment, a Digital Eye Width Monitor (DEWM) logic may be used to measure data eye width in real time. Other embodiments are also disclosed.

摘要翻译： 描述了通过使用相位内插器的精细训练来提高高速I / O（输入/输出）互连链路的系统定时裕度的方法和装置。 在一些实施例中，I / O链路使用正向时钟架构将数据从发射驱动器发送到接收机逻辑。 此外，在接收机侧，可以使用相位插值器（PI）逻辑将采样时钟放置在有效数据窗口或眼睛的中心。 在一个实施例中，可以使用数字眼睛宽度监视器（DEWM）逻辑来实时测量数据眼睛宽度。 还公开了其他实施例。

公开(公告)号：US08598910B1

公开(公告)日：2013-12-03

申请号：US13565083

申请日：2012-08-02

申请人： John Leshchuk ,  Joseph A. Manzella ,  Walter A. Roper

发明人： John Leshchuk ,  Joseph A. Manzella ,  Walter A. Roper

IPC分类号： H03K19/00 ,  H03K19/20 ,  H03K19/094 ,  H03K5/08 ,  H03L5/00 ,  H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： G06F1/14 ,  G06F1/08

摘要： In described embodiments, a timestamp generator includes a fixed clock domain driven by a fixed frequency clock, a core clock domain, coupled to the fixed clock domain, which is driven by a core clock whose frequency is adjustable during an operation of the timestamp generator. A timestamp logic operating in the core clock domain generates a timestamping output of the timestamp generator. A rate generator operating in both the fixed clock domain and the core clock domain generates per clock cycle increments in the fixed clock domain and transfers carry units from the fixed clock domain into the core clock domain, and a timestamp increment generation of the timestamp logic is clocked by the fixed frequency clock provided by the rate generator. A method for enabling timestamp in an ASIC to be accurate with system clock changes is also described.

摘要翻译： 在所描述的实施例中，时间戳发生器包括由固定频率时钟驱动的固定时钟域，耦合到固定时钟域的核心时钟域，其由在时间戳发生器的操作期间其频率可调节的核心时钟驱动。 在核心时钟域中工作的时间戳逻辑产生时间戳生成器的时间戳输出。 在固定时钟域和核心时钟域中工作的速率发生器在固定时钟域产生每个时钟周期的增量，并将进位单元从固定时钟域传送到核心时钟域，时间戳逻辑的时间戳增量生成 由速率发生器提供的固定频率时钟计时。 还描述了一种使ASIC中的时间戳准确地与系统时钟变化相关的方法。

公开(公告)号：US08537950B2

公开(公告)日：2013-09-17

申请号：US12851772

申请日：2010-08-06

申请人： Kwangseok Han ,  Marco Bruno ,  Stuart Aitken ,  Steve Jones ,  Simon Chang ,  James Digby Yarlet Collier

发明人： Kwangseok Han ,  Marco Bruno ,  Stuart Aitken ,  Steve Jones ,  Simon Chang ,  James Digby Yarlet Collier

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H04B17/104 ,  H04B17/00

摘要： Apparatus for controlling the generation of a DC signal at the output of a mixer, so that the DC signal is predictable, enabling a static offset compensation voltage to offset the DC signal. The apparatus comprises a mixer configured to receive a first and a second input signal, the mixer being such as to generate a first DC signal at the output of the mixer when the first and second input signals have the same frequency and a first relative phase, a phase detector for determining the relative phase of the first and second signals, and a phase modifier configured to modify the phase of the second signal relative to the first signal in dependence on the determination of the relative phase between the first and second signals such that the resulting DC signal at the output of the mixer is the first DC signal.

摘要翻译： 用于控制在混频器的输出处产生DC信号的装置，使得DC信号是可预测的，使静态偏移补偿电压能够抵消DC信号。 所述装置包括配置成接收第一和第二输入信号的混频器，所述混频器当所述第一和第二输入信号具有相同的频率和第一相对相位时，在所述混频器的输出处产生第一DC信号， 相位检测器，用于确定第一和第二信号的相对相位;以及相位修正器，被配置为根据第一和第二信号之间的相对相位的确定来相对于第一信号修改第二信号的相位，使得 混频器输出端产生的直流信号是第一个直流信号。

公开(公告)号：US08275083B2

公开(公告)日：2012-09-25

申请号：US11626213

申请日：2007-01-23

申请人： Joachim Ritter

发明人： Joachim Ritter

IPC分类号： H04L25/40

CPC分类号： H04L7/0331

摘要： An integrated circuit for an asynchronous serial data transfer comprises a sampler to sample the asynchronous serial data using a sampling clock. A bit length counter determines a bit time by counting a number (m) of predetermined clock cycles, where the bit length terminal variably adjusts the number (m) of clock cycles of the bit length counter.

摘要翻译： 用于异步串行数据传输的集成电路包括采样器，以使用采样时钟对异步串行数据进行采样。 位长度计数器通过对预定时钟周期的数量（m）进行计数来确定位时间，其中位长度端可变地调整位长度计数器的时钟周期数（m）。

公开(公告)号：US08189728B1

公开(公告)日：2012-05-29

申请号：US13108151

申请日：2011-05-16

申请人： Jingfeng Liu ,  Hongwei Song

发明人： Jingfeng Liu ,  Hongwei Song

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： G11B20/1816 ,  G11B20/10009 ,  G11B20/10444 ,  G11B2220/2541 ,  G11B2220/2562

摘要： A specialized structure measures clock-to-data jitter in an optical memory interface by averaging the result of two second-order estimates of zero crossing using measured signal values on either side of the zero crossing. In one embodiment, a first estimate uses two sample points before the zero crossing and one sample point after while the second estimate uses one sample point before the zero crossing and sample two points after.

摘要翻译： 专门的结构通过使用过零点两侧的测量信号值平均二交叉零二值估计的结果来测量光存储器接口中的时钟到数据抖动。 在一个实施例中，第一估计在过零之前使用两个采样点和一个采样点之后，而第二估计在过零点之前使用一个采样点，并且采样两点之后。

公开(公告)号：US08121240B1

公开(公告)日：2012-02-21

申请号：US10990045

申请日：2004-11-16

申请人： Ajay Dalvi

发明人： Ajay Dalvi

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H04L1/205 ,  G01R31/31709

摘要： Phase shift is added between a uttering clock signal and a data bit stream clocked by the clock signal. The phase shift is adjusted until half the data bits are captured (counted) over a measurement period. Adding this amount of phase shift between the clock and data signals centers the average clock edge placement. In a particular embodiment, counters, each having N bits where N is an integer, are used to count clock pulses and data bits. When one counter is full and the most-significant bit on the other counter goes high, the phase shift between the data and clock signal places the average clock edge at the data bit edge.

摘要翻译： 在发声时钟信号和由时钟信号定时的数据比特流之间增加相移。 调整相移，直到在测量周期内捕获（计数）数据位的一半。 在时钟和数据信号之间增加这种相移量将平均时钟边沿放置居中。 在特定实施例中，每个具有N位的计数器，其中N是整数，用于对时钟脉冲和数据位进行计数。 当一个计数器已满并且另一个计数器的最高有效位变为高电平时，数据和时钟信号之间的相移将平均时钟沿置于数据位沿。

公开(公告)号：USRE42829E1

公开(公告)日：2011-10-11

申请号：US11932846

申请日：2007-10-31

申请人： Jae Ryong Cho

发明人： Jae Ryong Cho

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： G11B20/10527 ,  G11B2020/1062 ,  G11B2020/1074 ,  G11B2020/10759 ,  G11B2220/2562 ,  H04N5/85 ,  H04N9/8063 ,  H04N21/4392

摘要： An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audio data signals contain normal data or invalid data. Invalid data is adjusted into normal audio data, and stored in the memory. The volume of the data stored in the memory is monitored to detect overflow and underflow conditions of the memory, a data transmitting stopping signal being sent during an overflow condition of the memory, a data transmitting requesting signal being sent during an underflow condition. The audio data reproduced from the memory is decoded, and the decoded audio data is output. Undesired errors are prevented by monitoring the reproduced audio data for invalid data and by adjusting invalid data into normal data when detected.

公开(公告)号：USRE42792E1

公开(公告)日：2011-10-04

申请号：US11932893

申请日：2007-10-31

申请人： Jae Ryong Cho

发明人： Jae Ryong Cho

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： G11B20/10527 ,  G11B2020/1062 ,  G11B2020/1074 ,  G11B2020/10759 ,  G11B2220/2562 ,  H04N5/85 ,  H04N9/8063 ,  H04N21/4392

摘要： An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audio data signals contain normal data or invalid data. Invalid data is adjusted into normal audio data, and stored in the memory. The volume of the data stored in the memory is monitored to detect overflow and underflow conditions of the memory, a data transmitting stopping signal being sent during an overflow condition of the memory, a data transmitting requesting signal being sent during an underflow condition. The audio data reproduced from the memory is decoded, and the decoded audio data is output. Undesired errors are prevented by monitoring the reproduced audio data for invalid data and by adjusting invalid data into normal data when detected.

摘要翻译： 用于补偿要记录在光盘上的音频信号的装置和方法，以优化音频解码电路中的存储器的使用，并且中和无效音频数据以产生良好的音频质量。 确定音频数据信号是否包含正常数据或无效数据。 将无效数据调整为正常音频数据，并存储在存储器中。 监视存储在存储器中的数据的容量以检测存储器的溢出和下溢条件，在存储器的溢出状态期间发送数据发送停止信号，在下溢条件期间发送数据发送请求信号。 从存储器再现的音频数据被解码，并且解码的音频数据被输出。 通过监视无效数据的再生音频数据，检测到无效数据成正常数据，可以防止不期望的错误。

公开(公告)号：US07945009B1

公开(公告)日：2011-05-17

申请号：US11838617

申请日：2007-08-14

申请人： Jingfeng Liu ,  Hongwei Song

发明人： Jingfeng Liu ,  Hongwei Song

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： G11B20/1816 ,  G11B20/10009 ,  G11B20/10444 ,  G11B2220/2541 ,  G11B2220/2562

摘要： A specialized structure measures clock-to-data jitter in an optical memory interface by averaging the result of two second-order estimates of zero crossing using measured signal values on either side of the zero crossing. In one embodiment, a first estimate uses two sample points before the zero crossing and one sample point after while the second estimate uses one sample point before the zero crossing and sample two points after. An existing clock associated with an internal analog-to-digital converter is used to evenly space the samples in time. To simplify the second-order estimate calculations, the three samples of the exemplary embodiment are give x values of −1, 0, and +1 respectively. Which of the two roots of the second-order estimates is used is based on the slope of the signal at the zero crossing.

摘要翻译： 专门的结构通过使用过零点两侧的测量信号值平均二交叉零二值估计的结果来测量光存储器接口中的时钟到数据抖动。 在一个实施例中，第一估计在过零之前使用两个采样点和一个采样点之后，而第二估计在过零点之前使用一个采样点，并且采样两点之后。 使用与内部模数转换器相关联的现有时钟来均匀地间隔样品。 为了简化二阶估计计算，示例性实施例的三个样本分别给出分别为-1,0和+1的x值。 使用二阶估计的两个根中的哪一个是基于过零点处的信号的斜率。