公开(公告)号：US12087364B2

公开(公告)日：2024-09-10

申请号：US17547856

申请日：2021-12-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masafumi Hayakawa

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/3445

Abstract: A semiconductor device includes a flash memory including a plurality of electrically erasable memory cells and configured to output a verification result signal indicating whether erasing is succeeded or not, and a control block configured to control the flash memory. The control block includes a batch erasing range control circuit indicating a collectively erased range in the flash memory. When the verification result signal VR indicates failure of erasing of sectors in a first range specified by the batch erasing range control circuit after the erasing is executed, a second range for which erasing is to be executed again is calculated on the basis of a failure sector address that specifies a sector for which the erasing is failed and an end sector address that specifies an end of the first range, the specified second range is set to the batch erasing range control circuit, and erasing sectors in the second range is executed.

公开(公告)号：US20240296891A1

公开(公告)日：2024-09-05

申请号：US18358635

申请日：2023-07-25

Applicant: Western Digital Technologies, Inc.

Inventor： Ming Wang ,  Liang Li ,  Xuan Tian

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/16 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102

Abstract: Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.

公开(公告)号：US12080772B2

公开(公告)日：2024-09-03

申请号：US18483466

申请日：2023-10-09

Applicant: SK hynix Inc.

Inventor： Sung Kun Park ,  Jae Young Song

IPC: H01L29/423 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41

CPC classification number: H01L29/42328 ,  G11C16/16 ,  G11C16/26 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  G11C16/3427

Abstract: A non-volatile memory device may include a substrate, a first floating gate, a second floating gate, a third floating gate and a fourth floating gate. The substrate may include an active region. The first to fourth floating gates may be formed on the substrate. The first to fourth floating gates may be radially arranged to be partially overlapped with the active region. The first floating gate and the third floating gate may face each other in a first direction. The first floating gate and the third floating gate may have asymmetrically planar shapes. The first floating gate and the second floating gate may face each other in a second direction substantially perpendicular to the first direction. The first floating gate and the second floating gate may have asymmetrically planar shapes. The third floating gate and the fourth floating gate may face each other in the second direction. The third floating gate and the fourth floating gate may have asymmetrically planar shapes. The fourth floating gate and the second floating gate may face each other in the first direction. The fourth floating gate and the second floating gate may have asymmetrically planar shapes.

公开(公告)号：US20240290406A1

公开(公告)日：2024-08-29

申请号：US18655700

申请日：2024-05-06

Applicant: Micron Technology, Inc.

Inventor： Rainer Frank BONITZ

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  G11C16/345

Abstract: A controller of a memory device may determine that an endurance parameter associated with a wear leveling pool of a memory of the memory device satisfies a threshold. The wear leveling pool includes a plurality of memory blocks of the memory. The controller may divide, based on determining that the endurance parameter satisfies the threshold, the plurality of memory blocks of the wear leveling pool into a first wear leveling pool subset that includes a first subset of the plurality of memory blocks and a second wear leveling pool subset that includes a second subset of the plurality of memory blocks. A first subset of a plurality of data partitions is stored in the first subset of the plurality of memory blocks, and a second subset of the plurality of data partitions is stored in the second subset of the plurality of memory blocks.

公开(公告)号：US20240282394A1

公开(公告)日：2024-08-22

申请号：US18231127

申请日：2023-08-07

Applicant: SK hynix Inc.

Inventor： Chang Beom WOO

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of memory strings, a peripheral circuit configured to perform an erase operation and a program operation on the memory block, and a control logic configured to control the peripheral circuit to perform the erase operation and the program operation on the memory block, wherein the control logic is configured to control the peripheral circuit to perform an abnormally injected electron removal operation that removes abnormally injected electrons trapped in a charge storage layer of a plurality of memory cells included in the memory block after the erase operation has been completed.

公开(公告)号：US12068042B2

公开(公告)日：2024-08-20

申请号：US17544260

申请日：2021-12-07

Applicant: SK keyfoundry Inc.

Inventor： Jin Hyung Kim ,  Sung Bum Park ,  Kee Sik Ahn

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/30 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

Abstract: A multi time program device with a power switch and a non-volatile memory implementing the power switch for multi time program is provided. The device performs a program operation or an erase operation of a non-volatile memory cell in a non-volatile memory device.

公开(公告)号：US20240273017A1

公开(公告)日：2024-08-15

申请号：US18644242

申请日：2024-04-24

Applicant: InnoGrit Technologies Co., Ltd.

Inventor： Bo Fu ,  Jie Chen

IPC: G06F12/02 ,  G06F12/0882 ,  G11C16/16

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/0882 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/2022 ,  G11C16/16

Abstract: Systems and methods are provided for data retrieval in garbage collection (GC) processes. A method may include obtaining column addresses based on bitmaps indicating positions of valid data units in respective pages within a plurality of blocks of a non-volatile storage device and issuing data transfer commands to the non-volatile storage device, the data transfer commands including the column addresses to identify valid data units of a page of data read into cache registers from the non-volatile storage device.

公开(公告)号：US12062397B2

公开(公告)日：2024-08-13

申请号：US17585261

申请日：2022-01-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Kha Nguyen ,  Hien Pham ,  Duc Nguyen

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/16 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30

Abstract: Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.

公开(公告)号：US12062393B2

公开(公告)日：2024-08-13

申请号：US17471597

申请日：2021-09-10

Applicant: KIOXIA CORPORATION

Inventor： Gou Fukano

IPC: G11C16/04 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C16/08 ,  G11C16/16 ,  H10B43/27 ,  H10B43/40

CPC classification number: G11C16/0483 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C16/08 ,  G11C16/16 ,  H10B43/27 ,  H10B43/40

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.

公开(公告)号：US20240265989A1

公开(公告)日：2024-08-08

申请号：US18605636

申请日：2024-03-14

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Steven Michael Kientz

IPC: G11C29/42 ,  G11C16/16 ,  G11C16/26 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C16/16 ,  G11C16/26 ,  G11C29/12015 ,  G11C29/44 ,  G11C2207/2254

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to detecting a triggering event, selecting a family of memory blocks of the memory device, the selected family being associated with a set of bins, each bin associated with a plurality of read voltage offsets to be applied to base read voltages during read operations. The operations performed by the processing device further include calibration operations to determine data state metric values characterizing application of read voltage offsets of various bins. The operations performed by the processing device further include identifying, based on the determined data state metrics, a target bin and associating the selected family with the target bin.