Reduced complexity non-binary LDPC decoding algorithm
    22.
    发明授权
    Reduced complexity non-binary LDPC decoding algorithm 有权
    降低复杂度的非二进制LDPC解码算法

    公开(公告)号:US08954820B2

    公开(公告)日:2015-02-10

    申请号:US13764649

    申请日:2013-02-11

    申请人: STEC, Inc.

    摘要: A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

    摘要翻译: 引入定制解码算法,结合相应的解码结构,以解决已知解码器的许多复杂性和大的存储器要求。 一个系统。 变量节点形成四个分量的置信向量,一个分量用于存储器单元的每个状态,并将当前主要分量(例如,最大的)传递到一个或多个校验节点。 校验节点基于从变量节点接收到的所有组件计算临时组件和相应的索引,它们传回给相应的变量节点。 变量节点基于从相应校验节点接收到的临时节点更新置信向量,并且基于置信度向量中的哪个组件当前是主要组件来确定对应的存储器单元的正确状态。

    APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN COMMUNICATION/ BROADCASTING SYSTEM
    23.
    发明申请
    APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN COMMUNICATION/ BROADCASTING SYSTEM 审中-公开
    在通信/广播系统中发送和接收数据的装置和方法

    公开(公告)号:US20150012803A1

    公开(公告)日:2015-01-08

    申请号:US14332017

    申请日:2014-07-15

    IPC分类号: H03M13/11 H03M13/00

    摘要: An apparatus and method for transmitting and receiving data in a wireless communication is provided. The method includes Low Density Parity Check (LDPC)-encoding LDPC information bits to generate a codeword, determining a number (Npunc) of bits to be punctured in parity bits of the codeword, determining a number (Npunc—group) of parity bit groups in which all bits are punctured, and puncturing the all bits within 0th to (Npunc—group−1)th parity bit groups indicated by a puncturing pattern, wherein the puncturing pattern is defined as an order of the parity bit groups defined as 29, 45, 43, 27, 32, 35, 40, 38, 0, 19, 8, 16, 41, 4, 26, 36, 30, 2, 13, 42, 46, 24, 37, 1, 33, 11, 44, 28, 20, 9, 34, 3, 17, 6, 21, 14, 23, 7, 22, 47, 5, 10, 12, 15, 18, 25, 31 and 39.

    摘要翻译: 提供了一种用于在无线通信中发送和接收数据的装置和方法。 该方法包括:将LDPC信息比特的低密度奇偶校验(LDPC)编码生成码字,确定要在码字的奇偶校验位中进行穿孔的比特数(Npunc),确定奇偶校验位组的数目(Npunc-group) 其中对所有比特进行删截,并对穿孔模式指示的第0到第(Npunc-group-1)个奇偶校验比特组中的所有比特进行穿孔,其中,删截图案被定义为定义为29的奇偶校验比特组的顺序, 45,43,27,32,35,40,38,0,19,8,16,41,4,26,36,30,2,13,42,46,24,37,1,33,11, 44,28,20,9,34,3,17,6,21,14,23,7,22,47,5,10,12,15,18,25,31及39条。

    Method and apparatus for decoding low density parity check code
    24.
    发明授权
    Method and apparatus for decoding low density parity check code 有权
    用于解码低密度奇偶校验码的方法和装置

    公开(公告)号:US08910011B2

    公开(公告)日:2014-12-09

    申请号:US13425840

    申请日:2012-03-21

    IPC分类号: H03M13/00 H03M13/11

    摘要: A low-density parity check (LDPC) code decoding method may be provided. The LDPC code decoding method may linearize or perform step-approximation on a natural logarithm hyperbolic cosine function included in a check node updating equation of a sum-product algorithm used for decoding an LDPC code, and may convert the linearized function to correspond to a check node updating equation of a min-sum algorithm.

    摘要翻译: 可以提供低密度奇偶校验(LDPC)码解码方法。 LDPC码解码方法可以对包含在用于解码LDPC码的和积算法的校验节点更新方程中的自然对数双曲余弦函数进行线性化或执行阶梯近似,并且可以将线性化函数转换成对应于检查 节点更新方程的最小和算法。

    REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM
    26.
    发明申请
    REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM 有权
    减少复杂非二进制LDPC解码算法

    公开(公告)号:US20130212451A1

    公开(公告)日:2013-08-15

    申请号:US13764649

    申请日:2013-02-11

    申请人: STEC, Inc.

    IPC分类号: H03M13/05

    摘要: A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

    摘要翻译: 引入定制解码算法,结合相应的解码结构,以解决已知解码器的许多复杂性和大的存储器要求。 一个系统。 变量节点形成四个分量的置信向量,一个分量用于存储器单元的每个状态,并将当前主要分量(例如,最大的)传递到一个或多个校验节点。 校验节点基于从变量节点接收到的所有组件计算临时组件和相应的索引,它们传回给相应的变量节点。 变量节点基于从相应校验节点接收到的临时节点更新置信向量,并且基于置信度向量中的哪个组件当前是主要组件来确定对应的存储器单元的正确状态。

    METHOD AND APPARATUS FOR DECODING LOW DENSITY PARITY CHECK CODE
    27.
    发明申请
    METHOD AND APPARATUS FOR DECODING LOW DENSITY PARITY CHECK CODE 有权
    解密低密度奇偶校验码的方法和装置

    公开(公告)号:US20120290891A1

    公开(公告)日:2012-11-15

    申请号:US13425840

    申请日:2012-03-21

    IPC分类号: H03M13/05 G06F11/10

    摘要: A low-density parity check (LDPC) code decoding method may be provided. The LDPC code decoding method may linearize or perform step-approximation on a natural logarithm hyperbolic cosine function included in a check node updating equation of a sum-product algorithm used for decoding an LDPC code, and may convert the linearized function to correspond to a check node updating equation of a min-sum algorithm.

    摘要翻译: 可以提供低密度奇偶校验(LDPC)码解码方法。 LDPC码解码方法可以对包含在用于解码LDPC码的和积算法的校验节点更新方程中的自然对数双曲余弦函数进行线性化或执行阶梯近似,并且可以将线性化函数转换成对应于检查 节点更新方程的最小和算法。

    METHOD AND SYSTEM TO IMPROVE THE PERFORMANCE AND/OR RELIABILITY OF A SOLID-STATE DRIVE
    28.
    发明申请
    METHOD AND SYSTEM TO IMPROVE THE PERFORMANCE AND/OR RELIABILITY OF A SOLID-STATE DRIVE 有权
    提高固态驱动器的性能和/或可靠性的方法和系统

    公开(公告)号:US20110320915A1

    公开(公告)日:2011-12-29

    申请号:US12825858

    申请日:2010-06-29

    申请人: JAWAD B. KHAN

    发明人: JAWAD B. KHAN

    摘要: A method and system to improve the performance and/or reliability of a solid-state drive (SSD). In one embodiment of the invention, the SSD has logic compress a block of data to be stored in the SSD. If it is not possible to compress the block of data below the threshold, the SSD stores the block of data without any compression. If it is possible to compress the block of data below the threshold, the SSD compresses the block of data and stores the compressed data in the SSD. In one embodiment of the invention, the SSD has logic to dynamically adjust or select the strength of the error correcting code of the data that is stored in the SSD. In another embodiment of the invention, the SSD has logic to provide intra-page XOR protection of the data in the page.

    摘要翻译: 一种提高固态硬盘(SSD)的性能和/或可靠性的方法和系统。 在本发明的一个实施例中,SSD具有逻辑压缩要存储在SSD中的数据块。 如果不可能压缩低于阈值的数据块,则SSD将不经任何压缩地存储数据块。 如果可以压缩低于阈值的数据块,则SSD压缩数据块并将压缩数据存储在SSD中。 在本发明的一个实施例中,SSD具有动态地调整或选择存储在SSD中的数据的纠错码的强度的逻辑。 在本发明的另一个实施例中,SSD具有为页面中的数据提供页内异或保护的逻辑。

    Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder
    29.
    发明申请
    Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder 有权
    重叠的基于子矩阵的LDPC(低密度奇偶校验)解码器

    公开(公告)号:US20100138721A1

    公开(公告)日:2010-06-03

    申请号:US12651453

    申请日:2010-01-01

    IPC分类号: H03M13/29 G06F11/10 H03M13/05

    摘要: Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

    摘要翻译: 重叠的基于子矩阵的LDPC(低密度奇偶校验)解码器。 提出了新的解码方法,通过该方法,立即采用对应于LDPC矩阵的子矩阵的更新的位边消息来更新与该子矩阵相对应的校验边消息,而不需要存储位边消息; 立即采用对应于LDPC矩阵的子矩阵的更新的校验边消息来更新与该子矩阵相对应的位边消息,而不需要存储校验边消息。 与执行整个LDPC矩阵的所有校验边消息的更新的系统相比,使用这种方法,在给定时间段内可以执行两倍的解码迭代,然后更新整个LDPC矩阵的所有位边消息,以及 所以。 当结合最小和处理执行这种重叠方法时,也可以节省大量的内存。

    ERROR CORRECTION CODING METHOD AND DEVICE
    30.
    发明申请
    ERROR CORRECTION CODING METHOD AND DEVICE 有权
    错误校正编码方法和设备

    公开(公告)号:US20090187810A1

    公开(公告)日:2009-07-23

    申请号:US12300412

    申请日:2007-04-25

    申请人: Norifumi Kamiya

    发明人: Norifumi Kamiya

    IPC分类号: H03M13/15 G06F17/10 G06F11/10

    摘要: An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m−r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths k1, k2, . . . , kr; a first arithmetic operation for performing polynomial multiplication on the (m−r) pieces of first blocks, and outputting r pieces of bit sequences having a length n; and a second arithmetic operation for performing a polynomial division and a polynomial multiplication on the r pieces of second blocks and r pieces of operation results of the first arithmetic operation, and outputting a bit sequence including redundant bit sequences having respective lengths n−k1, n−k2, . . . , n−kr.

    摘要翻译: 使用低密度奇偶校验码的纠错编码方法包括:将要进行纠错编码处理的信息比特序列划分为(mr)个第一块,每个第一块包括长度为n的比特序列和r个 第二块包括具有长度k1,k2,...的各个比特序列。 。 。 ,kr; 用于对(m-r)个第一块进行多项式乘法并输出具有长度为n的r个比特序列的第一算术运算; 以及第二算术运算,用于对第一运算结果的r个第二块和r个运算结果执行多项式除法和多项式乘法,并输出包括具有各自长度n-k1,n的冗余位序列的比特序列 -k2, 。 。 ,n-kr。