公开(公告)号：US08958492B1

公开(公告)日：2015-02-17

申请号：US13513154

申请日：2010-12-01

申请人： Norifumi Kamiya ,  Eisaku Sasaki

发明人： Norifumi Kamiya ,  Eisaku Sasaki

IPC分类号： H04L5/12

CPC分类号： H03M13/25 ,  H04L27/3411

摘要： By using circularly-arranged signal points obtained by rearranging a part of signal points arranged in a rectangular shape or a cross shape, average signal power and peak signal energy are reduced to improve nonlinear distortion characteristics. Provided is a bit mapping method in which an average value of a Hamming distance in terms of a specified lower bit portion between adjacent signal points is small, and a Euclidean distance between signal points at which the lower bit portions assigned thereto coincide with each other becomes maximum. By applying error correction code only to the lower bit portion, a data transmission method excellent in bit error rate characteristics is provided while suppressing a band expansion rate.

摘要翻译： 通过使用通过重排布置成矩形或十字形状的信号点的一部分而获得的循环布置的信号点，平均信号功率和峰值信号能量被减小以改善非线性失真特性。 提供了一种比特映射方法，其中相对于相邻信号点之间的指定低位部分的汉明距离的平均值较小，并且分配给其的低位部分彼此重合的信号点之间的欧几里德距离变为 最大值。 通过仅向较低位部分应用纠错码，在抑制频带扩展速率的同时提供了出错率特性优异的数据传输方法。

公开(公告)号：US20070300135A1

公开(公告)日：2007-12-27

申请号：US11792692

申请日：2005-11-29

申请人： Norifumi Kamiya

发明人： Norifumi Kamiya

IPC分类号： H03M13/19 ,  G06F11/10

CPC分类号： H04L1/005 ,  H03M13/116 ,  H03M13/118 ,  H04L1/0041 ,  H04L1/0057

摘要： An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical expression is used to perform an evaluation of the characteristic of an error floor area without using any computer experiments. In a polynomial multiplying block 1, (n−1)-th-order polynomial multiplying units (12-1 to 12-(m−1)) further divide an information bit string, which has been blocked for an error correction encoding, into (m−1) blocks having a length n and a single block having a length (n-r) (where m and n represent integers equal to or greater than two and where r represents an integer between 1 and n inclusive); receive blocks, which have the length n, of divided information bit strings; and output a series having the same length. An r-th-order polynomial dividing unit 2 receives an addition of the outputs from the respective (n−1)-th-order polynomial multiplying units (12-1 to 12-(m−1)) and also receives a block having the length (n-r), and outputs a redundant bit series having a length r.

摘要翻译： 一种纠错编码装置，其中装置结构简单; 使用迭代解码来实现接近于最佳精度的解码; 并且使用简单的数学表达式来执行错误楼面面积的特性的评估，而不使用任何计算机实验。 在多项式相乘块1中，（n-1）次多项式乘法单元（12-1〜12-（m-1））进一步将已被阻塞的用于纠错编码的信息位串划分成 （m-1）具有长度n的块（m和n表示等于或大于2的整数，并且其中r表示包括1和n之间的整数）的单个块; 具有长度为n的分割信息位串的接收块; 并输出具有相同长度的系列。 r阶多项式除法单元2接收来自各（n-1）次多项式乘法单元（12-1〜12 - （m-1））的输出的相加，并且还接收具有 长度（nr），并输出长度为r的冗余位序列。

公开(公告)号：US08713398B2

公开(公告)日：2014-04-29

申请号：US13823858

申请日：2012-03-22

申请人： Norifumi Kamiya

发明人： Norifumi Kamiya

IPC分类号： H03M13/00

CPC分类号： H03M13/15 ,  H03M13/116 ,  H03M13/1185 ,  H03M13/611 ,  H03M13/6561

摘要： Disclosed are an encoding apparatus for a quasi-cyclic low-density parity check code for calculating r×m-bit redundant data for information data of length k×m bits (k, m and r are positive integers), and a cyclic addition apparatus including a k×m-bit shift register and exclusive OR. With information data of a length of k×m×L bits (L≦k), a length of (r×m×(L+1)+k×m) bits is calculated as redundant data by adding redundant data of a length of r×m×L bits calculated using the encoding apparatus L times, k×m-bit data calculated by inputting the information data of a length of k×m×L bits to the cyclic addition apparatus, and r×m-bit redundant data calculated by inputting the k×m-bit data to the encoding apparatus.

摘要翻译： 公开了一种用于计算长度为k×m比特（k，m和r为正整数）的信息数据的r×m比特冗余数据的准循环低密度奇偶校验码的编码装置，以及循环加密装置 包括ak×m位移位寄存器和异或。 通过长度为k×m×L比特（L＆lt; ll; k）的信息数据，通过添加长度的冗余数据来计算长度（r×m×（L + 1）+ k×m）比特作为冗余数据 使用编码装置L倍计算的r×m×L比特，通过将k×m×L比特的长度的信息数据输入到循环加法装置而计算的k×m比特数据，以及r×m比特冗余 通过将k×m位数据输入到编码装置而计算的数据。

公开(公告)号：US20110219286A1

公开(公告)日：2011-09-08

申请号：US13119251

申请日：2009-11-06

申请人： Norifumi Kamiya

发明人： Norifumi Kamiya

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/116 ,  H03M13/1122 ,  H03M13/1137 ,  H03M13/6505 ,  H03M13/6566

摘要： A decoding device comprises two check node processing devices of feedback shift register type, each of which node processing includes a plurality of registers and a plurality of comparator circuits. A multiplexer and a demultiplexer switch between the two check node processing devices, and a memory holds the two sorts of data. The comparator circuits are interposed between registers of the check node processing device.

摘要翻译： 解码装置包括反馈移位寄存器类型的两个校验节点处理装置，每个节点处理包括多个寄存器和多个比较器电路。 在两个校验节点处理设备之间的多路复用器和解复用器切换，并且存储器保存两种数据。 比较电路插在校验节点处理装置的寄存器之间。

公开(公告)号：US20100251063A1

公开(公告)日：2010-09-30

申请号：US12744516

申请日：2008-10-28

申请人： Norifumi Kamiya

发明人： Norifumi Kamiya

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1111 ,  H03M13/6505

摘要： A data converting means generates first interim data held in one-to-one correspondence to columns vectors from data stored in a first storage means and data stored in a second storage means. A check node processing means generates second interim data for updating the data stored in the first storage means based on the sum of the first interim data and received data. The data converting means updates the data stored in the second storage means using the first interim data, and updates the data stored in the first storage means using the second interim data generated by the check node processing means. Decoded data are generated by a process carried out by the data converting means and the check node processing means.

摘要翻译： 数据转换装置产生与存储在第一存储装置中的数据和存储在第二存储装置中的数据的列向量一一对应保存的第一中间数据。 校验节点处理装置根据第一临时数据和接收数据之和生成用于更新存储在第一存储装置中的数据的第二临时数据。 数据转换装置使用第一中间数据更新存储在第二存储装置中的数据，并且使用由校验节点处理装置生成的第二中间数据来更新存储在第一存储装置中的数据。 解码的数据由数据转换装置和校验节点处理装置执行的处理生成。

公开(公告)号：US20120089884A1

公开(公告)日：2012-04-12

申请号：US13139785

申请日：2009-12-11

申请人： Norifumi Kamiya

发明人： Norifumi Kamiya

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/116 ,  H03M13/1111

摘要： Provided is an encoding apparatus wherein a transmission data sequence is divided into L short sequences, each of which is then encoded by use of an m-stage pseudo-cyclic low-density parity check encoding system. Each of the L encoded sequences is further divided into shorter sequences, the number of which is identical to the number m of the stages of the pseudo-cyclic codes and each of which has a length m. The shorter sequences are rearranged in order by a replacing module, thereafter encoded, by use of the m-stage pseudo-cyclic low-density parity check encoding system, and outputted. Accordingly, a decoding apparatus with a simple structure where node processing circuits (e.g., minimum-value calculating circuits), the number of which is p that is a submultiple of the number m of the foregoing stages, are provided, can be employed to efficiently decode the codes having a large frame length and a large encoding gain.

摘要翻译： 提供了一种编码装置，其中传输数据序列被划分为L个短序列，然后通过使用m级伪循环低密度奇偶校验编码系统对其进行编码。 L个编码序列中的每一个被进一步划分成较短的序列，其数量与伪循环码的级数m相同，并且每个具有长度m。 较短的序列通过替换模块按顺序重新排列，然后通过使用m级伪循环低密度奇偶校验编码系统进行编码并输出。 因此，可以使用具有简单结构的解码装置，其中节点处理电路（例如，最小值计算电路）的数量p是上述级的数量m的p的数量，可以被有效地 解码具有大帧长度和较大编码增益的码。

公开(公告)号：US08074142B2

公开(公告)日：2011-12-06

申请号：US12088142

申请日：2006-09-21

申请人： Norifumi Kamiya

发明人： Norifumi Kamiya

IPC分类号： G06F11/00

CPC分类号： H03M13/658 ,  H03M13/1117 ,  H03M13/1122 ,  H03M13/1134 ,  H03M13/116 ,  H03M13/6505

摘要： A decoding apparatus for low density parity check codes includes a variable-to-check message generator and a check-to-variable message generator. The variable-to-check message generator includes a variable-to-check processing unit block, provided with an adder, and which is arranged between registers corresponding to locations of ‘1’s in a check matrix. The check-to-variable message generator includes a check-to-variable processing unit block, provided with a comparator, between registers corresponding to locations of ‘1’s in the check matrix. The decoding apparatus for low density parity check codes is simple in configuration and is able to perform high speed processing without using RAMs without the necessity of performing complex control operations.

摘要翻译： 用于低密度奇偶校验码的解码装置包括可变检查消息发生器和可变消息发生器。 可变检查消息发生器包括具有加法器的可变检查处理单元块，并且被布置在与检查矩阵中的'1'的位置相对应的寄存器之间。 该校验变量消息生成器包括在对应于校验矩阵中的'1'的位置的寄存器之间提供有比较器的校验变量处理单元块。 用于低密度奇偶校验码的解码装置结构简单，并且能够在不使用RAM的情况下执行高速处理，而不需要执行复杂的控制操作。

公开(公告)号：US07979780B2

公开(公告)日：2011-07-12

申请号：US11792692

申请日：2005-11-29

申请人： Norifumi Kamiya

发明人： Norifumi Kamiya

IPC分类号： H03M13/00

CPC分类号： H04L1/005 ,  H03M13/116 ,  H03M13/118 ,  H04L1/0041 ,  H04L1/0057

摘要： An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical expression is used to perform an evaluation of the characteristic of an error floor area without using any computer experiments. In a polynomial multiplying block 1, (n−1)-th-order polynomial multiplying units (12-1 to 12-(m−1)) further divide an information bit string, which has been blocked for an error correction encoding, into (m−1) blocks having a length n and a single block having a length (n−r) (where m and n represent integers equal to or greater than two and where r represents an integer between 1 and n inclusive); receive blocks, which have the length n, of divided information bit strings; and output a series having the same length. An r-th-order polynomial dividing unit 2 receives an addition of the outputs from the respective (n−1)-th-order polynomial multiplying units (12-1 to 12-(m−1)) and also receives a block having the length (n−r), and outputs a redundant bit series having a length r.

摘要翻译： 一种纠错编码装置，其中装置结构简单; 使用迭代解码来实现接近于最佳精度的解码; 并且使用简单的数学表达式来执行错误楼面面积的特性的评估，而不使用任何计算机实验。 在多项式相乘块1中，（n-1）次多项式乘法单元（12-1至12-（m-1））进一步将已被阻塞用于纠错编码的信息位串划分为 （n-r）（其中m和n表示等于或大于2的整数，并且其中r表示1和n之间的整数）（m-1）具有长度为n的块和具有长度（n-r） 具有长度为n的分割信息位串的接收块; 并输出具有相同长度的系列。 r阶多项式除法单元2接收来自第（n-1）次多项式乘法单元（12-1〜12-（m-1））的输出的相加，并且还接收具有 长度（n-r），并输出具有长度r的冗余位序列。

公开(公告)号：US20090187810A1

公开(公告)日：2009-07-23

申请号：US12300412

申请日：2007-04-25

申请人： Norifumi Kamiya

发明人： Norifumi Kamiya

IPC分类号： H03M13/15 ,  G06F17/10 ,  G06F11/10

CPC分类号： H03M13/11 ,  G11B20/18 ,  H03M13/1151 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1168 ,  H03M13/611 ,  H03M13/617 ,  H03M13/6561

摘要： An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m−r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths k1, k2, . . . , kr; a first arithmetic operation for performing polynomial multiplication on the (m−r) pieces of first blocks, and outputting r pieces of bit sequences having a length n; and a second arithmetic operation for performing a polynomial division and a polynomial multiplication on the r pieces of second blocks and r pieces of operation results of the first arithmetic operation, and outputting a bit sequence including redundant bit sequences having respective lengths n−k1, n−k2, . . . , n−kr.

摘要翻译： 使用低密度奇偶校验码的纠错编码方法包括：将要进行纠错编码处理的信息比特序列划分为（mr）个第一块，每个第一块包括长度为n的比特序列和r个 第二块包括具有长度k1，k2，...的各个比特序列。 。 。 ，kr; 用于对（m-r）个第一块进行多项式乘法并输出具有长度为n的r个比特序列的第一算术运算; 以及第二算术运算，用于对第一运算结果的r个第二块和r个运算结果执行多项式除法和多项式乘法，并输出包括具有各自长度n-k1，n的冗余位序列的比特序列 -k2， 。 。 ，n-kr。

公开(公告)号：US08910014B2

公开(公告)日：2014-12-09

申请号：US13640568

申请日：2011-04-19

申请人： Norifumi Kamiya

发明人： Norifumi Kamiya

IPC分类号： H03M13/00 ,  H03M13/11 ,  H03M13/03

CPC分类号： H03M13/116 ,  H03M13/033 ,  H03M13/1188

摘要： A coding device includes: an inspection matrix generating module that generates a block inspection matrix; and a coding module that generates and outputs a code word from an input message by the inspection matrix. The inspection matrix generating module includes: a degree-allocation unit that prescribes function values of the block inspection matrix by the coefficients of a self-reciprocal polynomial expression; a weight distribution determination unit that prescribes the number of components that are non-zero matrices among the components of each block of the block inspection matrix using a mask pattern; a first degree-altering unit that considers the sum of the components of the k_r-th row block of the block inspection matrix as a cyclic permutation matrix; and a second degree-altering unit that prescribes the row-block number of components that are non-zero matrices among the components of each row block excluding said k_r-th row block of the clock inspection matrix.

摘要翻译： 编码装置包括：生成块检查矩阵的检查矩阵生成模块; 以及编码模块，其通过检查矩阵从输入消息生成和输出码字。 检查矩阵生成模块包括：度分配单元，其通过自相关多项式表达式的系数来规定块检查矩阵的函数值; 权重分布确定单元，其使用掩模图案来规定块检查矩阵的每个块的分量中的非零矩阵的分量的数量; 考虑块检查矩阵的第k_r行块的分量之和作为循环置换矩阵的第一变化单元; 以及第二改变单元，其规定了除了时钟检查矩阵的所述第k_r行块之外的每个行块的分量之中的非零矩阵的分组的行块数。