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149 条记录 (耗时 0.013 秒)

    Low power logic circuit with storage charge control for fast switching
    23.
    发明授权
    Low power logic circuit with storage charge control for fast switching 失效
    低功耗逻辑电路具有存储充电控制功能，可快速切换

    公开(公告)号：US4626710A

    公开(公告)日：1986-12-02

    申请号：US719943

    申请日：1985-04-04

    申请人： Siegfried K. Wiedmann

    发明人： Siegfried K. Wiedmann

    IPC分类号： H01L27/082 ,  H01L21/8222 ,  H01L27/06 ,  H03K19/013 ,  H03K19/084

    CPC分类号： H03K19/084 ,  H01L27/067 ,  H03K19/013

    摘要： A bipolar logic circuit with superior speed/power characteristics is described. Circuit operation is based on a unique dynamic minority carrier charge exchange mechanism between the input diodes performing the logic and the oppositely poled level shift diode(s) at the input of the transistor output stage. To accomplish this, the input or logic diodes as well as the level shift diode(s) are laid out as large .tau..sub.s diodes with .tau..sub.s being the minority carrier charge storage time constant. Thus, despite very small dc currents during static operation (resulting in an extremely small dc power dissipation) high dynamic switching currents for turning-off as well as for turning-on the output transistors are achieved.

    摘要翻译： 描述了具有优越速度/功率特性的双极逻辑电路。 电路操作基于在晶体管输出级的输入端执行逻辑的输入二极管与反极化电平移位二极管之间的独特的动态少数载流子电荷交换机制。 为了实现这一点，输入或逻辑二极管以及电平移位二极管被布置为大tau的二极管，其中τs是少数载流子电荷存储时间常数。 因此，尽管在静态操作期间具有非常小的直流电流（导致非常小的直流功率耗散），但是实现用于关断以及导通输出晶体管的高动态开关电流。

    Calculator with provision for automatically interposing memory accesscycles between other wise regularly recurring logic cycles
    24.
    发明授权
    Calculator with provision for automatically interposing memory accesscycles between other wise regularly recurring logic cycles 失效
    计算器提供自动访问其他正常循环逻辑周期之间的存储器访问

    公开(公告)号：US3769621A

    公开(公告)日：1973-10-30

    申请号：US3769621D

    申请日：1971-08-25

    申请人： HEWLETT PACKARD CO

    发明人： OSBORNE T

    IPC分类号： G01R31/3185 ,  G06F1/32 ,  G06F3/02 ,  G06F3/153 ,  G06F7/00 ,  G06F9/40 ,  G06F11/273 ,  G06F11/32 ,  G06F11/36 ,  G06F13/00 ,  G06F15/02 ,  G09G1/18 ,  H03K19/084 ,  H03M11/22 ,  G06F9/00

    CPC分类号： H03M11/22 ,  G01R31/318525 ,  G06F1/3203 ,  G06F1/3287 ,  G06F3/02 ,  G06F3/0227 ,  G06F3/153 ,  G06F7/00 ,  G06F9/4425 ,  G06F11/273 ,  G06F11/325 ,  G06F13/00 ,  G06F15/02 ,  G09G1/18 ,  H03K19/084 ,  Y02D10/171

    摘要： Internal control and subroutine logic transfers data between a keyboard input, a random access memory, and a plurality of flipflop registers to perform arithmetic operations and transfers the results of these operations to a cathode ray tube output display. The flip-flop registers include a program register comprising a set of primary flip-flops for designating a subroutine to be performed and a set of secondary flip-flops for sequentially designating a group of one or more instructions to be executed in each state of the designated subroutine. The primary and secondary flip-flops are controlled by multiple feedback paths. Power switching is employed in the internal control and subroutine logic so that the subroutines and instructions are supplied with power only when they are to be executed. The flipflop registers also include a memory access register for receiving information read from and to be written into the random access memory. When a random access memory cycle is required, it is automatically interposed between the otherwise regularly recurring logic cycles by the internal control and subroutine logic. Separate logic circuits are provided for enabling the state of the secondary flip-flops to be directly transferred to the memory access register and vice versa so that encoded transfer vectors may be stored in the random access memory and subsequently decoded by the internal control and subroutine logic to permit unrestricted subroutine returns. In the keyboard input, two power supply returns are employed to define one bit of the keyboard encoder. The random access memory is partitioned into one portion addressed by a single bit in an address register and into another, larger portion addressed by the remaining bits in the address register. Each flip-flop of the machine is a J-K flip-flop provided with an adjustable threshold for noise immunity and with a high internal gain on the J-K inputs. In the cathode ray tube output display a recurring pattern generated by integration in only two directions is selectively blanked to display the results of the operations performed by the calculator. A tester may be connected to the machine for allowing all subroutines to be operated in a single step mode. The tester is provided with switches for initializing any internal state of the machine or stopping normal execution under any prescribed conditions and with apparatus for accessing the random access memory.