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公开(公告)号：US20220399860A1
公开(公告)日：2022-12-15
申请号：US17838204
申请日：2022-06-11
Applicant: SiliconIntervention Inc.
Inventor： A. Martin Mallinson
Abstract: An apparatus and method for improving the efficiency of a D class amplifier, particularly at lower output levels. A class D amplifier having a load with inductance, such as a transducer, is configured to concurrently act as its own buck regulator. A capacitor connected to ground and to both ends of the transducer through switches functions as the buck regulator in connection with the inductance of the transducer, providing the class D amplifier with additional voltage levels such as might be provided by a G/H class amplifier but without the added complexity or expense of the G/H configurations. Better efficiency is possible than that provided by a 100% efficient conventional buck regulator. No envelope detector is required, nor any change to the gain of the digital signal to the class D amplifier. Feedback may be used if desired, but is not required to obtain a high quality output signal.
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公开(公告)号：US11354237B2
公开(公告)日：2022-06-07
申请号：US16821191
申请日：2020-03-17
Applicant: SiliconIntervention Inc.
Inventor： A. Martin Mallinson , Christian Leth Petersen
Abstract: A multiport memory in which one of the ports is analog rather than digital is described. In one embodiment, the analog port functions as a read-only port and the digital port functions as a write only port. This allows the data in the core memory to be applied to an analog signal, while retaining a digital port having access to the core memory for rapid storage of data. One potential use of such a multiport memory is as a bridge between a digital computer and an analog computer; for example, this allows a digitally programmed two-port memory to derive a sum-of-products signal from a plurality of analog input signals, and a plurality of such multiport memories to be used in an analog neural network such as a programmable neural net implementing analog artificial intelligence (AI).
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公开(公告)号：US10965311B2
公开(公告)日：2021-03-30
申请号：US16825958
申请日：2020-03-20
Applicant: SiliconIntervention Inc.
Inventor： A. Martin Mallinson
Abstract: Described herein is an improved apparatus for increasing the performance of a ΣΔ modulator, which may function as an ADC. In one embodiment, the ΣΔ modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the ΣΔ modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.
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公开(公告)号：US10680638B2
公开(公告)日：2020-06-09
申请号：US16503553
申请日：2019-07-04
Applicant: SiliconIntervention Inc.
Inventor： A. Martin Mallinson
Abstract: Described herein is a method and apparatus for reducing ISI in a single-bit ΣΔ modulator without reducing the dynamic range of the modulator. In one embodiment, the signal fed back to the input of the modulator is not the single-bit outputs of a quantizer as in the prior art, but rather patterns of such outputs. The patterns are selected so that each pattern has the same number of transition edges and there is thus no mismatch of transition times. In one embodiment, the patterns are created by digital logic. In another embodiment, an analog signal is added to the error signal in the feedback loop which causes the quantizer to generate the patterns. When the amplitude of the input signal exceeds a certain level, the modulator reverts to the typical operation of a prior art modulator, thus preserving the full dynamic range of the modulator.
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公开(公告)号：US12052025B2
公开(公告)日：2024-07-30
申请号：US18077949
申请日：2022-12-08
Applicant: SiliconIntervention Inc.
Inventor： A. Martin Mallinson
IPC: H03M1/00 , G06F5/01 , G06F7/02 , H03F3/04 , H03F3/183 , H03F3/45 , H03G3/00 , H03K5/24 , H03M1/34 , H03M1/36 , H03M1/06
CPC classification number: H03M1/002 , G06F5/01 , G06F7/02 , H03F3/04 , H03F3/183 , H03F3/45089 , H03F3/45475 , H03G3/001 , H03K5/24 , H03M1/34 , H03M1/365 , H03F2203/45528 , H03M1/0682
Abstract: An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.
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Patent Agency Ranking
公开(公告)号：US20230196064A1
公开(公告)日：2023-06-22
申请号：US17818228
申请日：2022-08-08
Applicant: SiliconIntervention Inc.
Inventor： A. Martin Mallinson
IPC: G06N3/04
CPC classification number: G06N3/04
Abstract: An analog element for use as a neuron in a recurrent neural network is described, the analog element having memory of a prior layer state and being a continuous time circuit rather than having a discrete clocking interval. The element is characterized and described by the Laplace s-domain operator, as distinct from a digital solution that uses the z-domain operator appropriate for quantized time descriptions. Rather than using an all-pass filter, the analog equivalent of a unit delay in the z-domain, a finite gain integrator, which is a simpler circuit, may be used to provide the delay in the analog s-domain. The resulting circuit may be easily implemented at the transistor level.
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公开(公告)号：US20230185872A1
公开(公告)日：2023-06-15
申请号：US18080557
申请日：2022-12-13
Applicant: SiliconIntervention Inc.
Inventor： A. Martin Mallinson
IPC: G06F17/14
CPC classification number: G06F17/142
Abstract: A method for performing a fast Fourier transform. The bin spreading effect of conventional FFT methodology may be removed by a mathematical technique that relies on an incomplete replacement of the input data sequence. In the present approach this replacement is accomplished by a “round robin” method. In this approach no window function is required and the FFT calculation proceeds after each new sample is added round robin fashion to the input sequence. The resulting output bins from the FFT show the signal evolution with time, overlapping as in the known art but by a single sample. The output of a FFT so constructed is not time invariant, but rather there is a rotation present in each output bin when viewed as an analytical signal. This rotation is predictable and hence removeable, but is also exploitable as a means to remove the bin spill over.
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公开(公告)号：US11514302B2
公开(公告)日：2022-11-29
申请号：US16806264
申请日：2020-03-02
Applicant: SiliconIntervention Inc.
Inventor： A. Martin Mallinson
Abstract: A programmable impedance element consists of a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches, the two-port elements arranged in a chain fashion with a structured set of switches such that a range of impedances can be obtained from each cell by dynamically changing the connections between the impedance elements in the cell. The common cell is constructed by connecting the nominally identical two-port impedance elements in a way that the number of possible combinations of the impedance elements is reduced to the subset of all possible combinations that uses the minimum possible number of connections. This structure allows the creation of matched impedances using industry standard devices. The connections between impedance elements are switches that may be “field-programmable,” i.e., that may be set on the chip after manufacture and configured during operation of the circuit, or alternatively may be mask programmable.
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公开(公告)号：US11513596B2
公开(公告)日：2022-11-29
申请号：US16849794
申请日：2020-04-15
Applicant: SiliconIntervention Inc.
Inventor： A. Martin Mallinson
Abstract: Described herein is a system and method for controlling a computing system by an AI network based upon an electroencephalograph (EEG) signal from a user. The user's EEG signals are first detected as the user operates an existing controller, during which time the associated artificial intelligence (AI) system learns by correlating the EEG signals with the commands received from the controller. Once the AI system determines that there is sufficient correlation to predict the user's actions, it can take control of the computing system and initiate commands based upon the user's EEG signal in place of the user's actions with the controller. At this point, weights in the AI network may be locked so that further commands from the controller, or the lack thereof, do not reduce correlation with the EEG signals. In some embodiments, the AI network may initiate commands faster than the user would be able to do.
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公开(公告)号：US11481601B2
公开(公告)日：2022-10-25
申请号：US16806980
申请日：2020-03-02
Applicant: SiliconIntervention Inc.
Inventor： A. Martin Mallinson
IPC: G06N3/04
Abstract: An analog element for use as a neuron in a recurrent neural network is described, the analog element having memory of a prior layer state and being a continuous time circuit rather than having a discrete clocking interval. The element is characterized and described by the Laplace s-domain operator, as distinct from a digital solution that uses the z-domain operator appropriate for quantized time descriptions. Rather than using an all-pass filter, the analog equivalent of a unit delay in the z-domain, a finite gain integrator, which is a simpler circuit, may be used to provide the delay in the analog s-domain. The resulting circuit may be easily implemented at the transistor level.
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