公开(公告)号：US06806521B2

公开(公告)日：2004-10-19

申请号：US10338138

申请日：2003-01-08

Applicant: Dun-Nian Yaung ,  Kuo-Ching Huang

Inventor： Dun-Nian Yaung ,  Kuo-Ching Huang

IPC: H01L31062

CPC classification number: H01L27/15 ,  H01L33/0004

Abstract: A new method and structure for the combined creation of CMOS devices and LED devices. The process starts with a substrate over the surface of which are designated a first surface region for the creation of CMOS devices there-over and a second surface region for the creation of LED devices there-over. A relatively thick layer of gate oxide is created over the surface of the substrate. The first surface region is blocked by a mask of photoresist after which the second surface region is exposed to a plasma etch, thereby providing roughness to the surface of the relatively thick layer of gate oxide and reducing the thickness thereof. The blocking mask is removed, additional oxidation of the exposed surface creates a relatively thick layer of gate oxide over the first surface area and a relatively thin layer of gate oxide over the second surface area.

Abstract translation: 一种用于组合创建CMOS器件和LED器件的新方法和结构。 该过程从其表面上的衬底指定为用于在其上形成CMOS器件的第一表面区域和用于在其上形成LED器件的第二表面区域开始。 在衬底的表面上形成较厚的栅极氧化层。 第一表面区域被光致抗蚀剂掩模阻挡，之后第二表面区域暴露于等离子体蚀刻，从而为栅极氧化物的较厚层的表面提供粗糙度并减小其厚度。 去除阻挡掩模，暴露表面的额外氧化在第一表面区域上形成相对厚的栅极氧化物层，并在第二表面区域上形成相当薄的栅极氧化物层。

公开(公告)号：US06194234B1

公开(公告)日：2001-02-27

申请号：US09324925

申请日：1999-06-04

Applicant: Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Yu-Hua Lee

Inventor： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Yu-Hua Lee

IPC: G01R3126

CPC classification number: H01L22/12

Abstract: A new method based on measuring the weight of a wafer (on which the layer of HSG has been deposited) before (W1) and after (W2) the surface of the HSG layer is coated with a layer of either photoresist or SOG. The difference delta W=W2−W1 provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG. This new method can also be based on measuring the weight W of rejected or dropped PR or SOG after the surface of the HSG layer has been coated with a layer of either photoresist or SOG. The weight of the rejected or dropped PR or SOG also provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG.

Abstract translation: 基于测量在HSG层的表面之前（W1）和之后（W2）的晶片（其上沉积了HSG的层）的重量的新方法涂覆有光致抗蚀剂或SOG层。 差值ΔW= W2-W1提供HSG沉积层的表面的粗糙度或平滑度的指标。 这种新方法也可以基于测量在HSG层的表面已经涂覆有光致抗蚀剂或SOG层之后的被拒绝或掉落的PR或SOG的重量W。 拒收或掉落的PR或SOG的重量也提供HSG沉积层的表面的粗糙度或平滑度的指标。

公开(公告)号：US07619166B2

公开(公告)日：2009-11-17

申请号：US11136558

申请日：2005-05-25

Applicant: Kuo-Ching Huang ,  Yu-Cheng Chang

Inventor： Kuo-Ching Huang ,  Yu-Cheng Chang

IPC: H01B7/08

CPC classification number: H05K1/147 ,  H04N1/00519 ,  H04N1/1017 ,  H04N1/193 ,  H04N2201/0081 ,  H05K1/144 ,  H05K2201/09109

Abstract: A bus structure may include two or more soft buses and one or more soft separation layers. The two or more soft buses may be stacked side by side with respect to each other. The one or more soft separation layers may be sandwiched between two adjacent soft buses of the two or more soft buses.

Abstract translation: 总线结构可以包括两个或更多个软总线和一个或多个软分离层。 两个以上的软总线可以相对于彼此并排堆叠。 一个或多个软分离层可以夹在两个或多个软总线的两个相邻的软总线之间。

公开(公告)号：US20070129189A1

公开(公告)日：2007-06-07

申请号：US11332340

申请日：2006-01-17

Applicant: Kuo-Ching Huang ,  Yu-Cheng Chang

Inventor： Kuo-Ching Huang ,  Yu-Cheng Chang

IPC: F16H7/18 ,  F16H7/08

CPC classification number: F16H7/08 ,  F16H2007/0806 ,  F16H2007/0812

Abstract: A belt tension adjustment mechanism for use in an optical module of a scanning apparatus includes a sliding member, a fixture member, a supporting member and a resilient member. The sliding member is arranged on a surface of the optical module and movable on the surface of the optical module. The fixture member is used to fix the belt. The supporting member supports the belt. By means of the resilient member, a tension is applied onto the belt.

Abstract translation: 用于扫描装置的光学模块中的皮带张力调节机构包括滑动构件，固定构件，支撑构件和弹性构件。 滑动构件布置在光学模块的表面上并且可在光学模块的表面上移动。 固定件用于固定皮带。 支撑构件支撑带。 通过弹性构件，张力被施加到带上。

公开(公告)号：US20060164531A1

公开(公告)日：2006-07-27

申请号：US11044922

申请日：2005-01-27

Applicant: Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

Inventor： Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

IPC: H04N5/335

CPC classification number: H04N5/361 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H04N5/3559 ,  H04N5/374 ,  H04N5/37452

Abstract: A CMOS image sensor having increased capacitance that allows a photo-diode to generate a larger current is provided. The increased capacitance reduces noise and the dark signal. The image sensor utilizes a transistor having nitride spacers formed on a buffer oxide layer. Additional capacitance may be provided by various capacitor structures, such as a stacked capacitor, a planar capacitor, a trench capacitor, a MOS capacitor, a MIM/PIP capacitor, or the like. Embodiments of the present invention may be utilized in a 4-transistor pixel or a 3-transistor pixel configuration.

Abstract translation: 提供了具有允许光电二极管产生较大电流的增加的电容的CMOS图像传感器。 增加的电容可以降低噪声和暗信号。 图像传感器利用形成在缓冲氧化物层上的具有氮化物间隔物的晶体管。 附加电容可以由诸如叠层电容器，平面电容器，沟槽电容器，MOS电容器，MIM / PIP电容器等的各种电容器结构来提供。 本发明的实施例可以用于4-晶体管像素或3-晶体管像素配置。

公开(公告)号：US06880675B2

公开(公告)日：2005-04-19

申请号：US10423607

申请日：2003-04-25

Applicant: Kuo-Ching Huang

Inventor： Kuo-Ching Huang

IPC: E06C1/18 ,  E06C1/22 ,  E06C7/08 ,  E06C1/00

CPC classification number: E06C7/083 ,  E06C1/18 ,  E06C1/22

Abstract: A ladder assembly includes two symmetric support stands pivotally connected with each other. Each of the two support stands includes a main frame, an upper frame, a lower frame, a top bar, a retraction control unit, and four fixing devices. Thus, height of the ladder assembly can be adjusted easily and conveniently, thereby facilitating the user operating the ladder assembly. In addition, the upper frame and the lower frame can be folded on the main frame, so as to reduce the volume the ladder assembly efficiently, thereby greatly facilitating storage and transportation of the ladder assembly.

Abstract translation: 梯子组件包括彼此枢转连接的两个对称支撑架。 两个支撑台中的每一个包括主框架，上框架，下框架，顶杆，缩回控制单元和四个固定装置。 因此，可以容易且方便地调整梯子组件的高度，从而便于使用者操作梯子组件。 此外，上框架和下框架可以折叠在主框架上，以便有效地减少梯子组件的体积，从而极大地方便了梯子组件的存储和运输。

公开(公告)号：US06661043B1

公开(公告)日：2003-12-09

申请号：US10400401

申请日：2003-03-27

Applicant: Kuo-Ching Huang ,  Wen-Cheng Chen ,  Wen-Chuan Chiang ,  Kuo-Chuang Tseng

Inventor： Kuo-Ching Huang ,  Wen-Cheng Chen ,  Wen-Chuan Chiang ,  Kuo-Chuang Tseng

IPC: H01L218242

CPC classification number: H01L27/1085 ,  H01L27/1087

Abstract: A new method is provided for the creation of a 1T RAM cell. Standard processing is applied to create STI trenches in the surface of a substrate, N2 implantations are performed into the sidewalls of the STI trenches. A layer of lining oxide is created, the implanted N2 interacts with the lining oxide to form SiON over exposed surfaces of the STI trenches. STI oxide is deposited and polished, filling the STI trenches there-with. Crown patterning is performed to define capacitor areas, the crown patterning stops on a layer of etch stop material and the created SION and partially removes STI oxide from the STI trenches. Layers of etch stop material, exposed SiON and pad oxide are removed, exposing the surface of the silicon substrate, the etched layers of STI oxide are not affected by this removal. A layer of SAC oxide is grown, n-well and p-well implantations are performed into the surface of the substrate. The layer of SAC oxide is removed, gate oxide is grown, polysilicon is deposited and patterned and etched, forming polysilicon gate material and polysilicon top plate of the capacitor. Standard processing is further applied to complete the 1T-RAM cell by providing gate spacers and impurity implantations for the gate electrode, by saliciding contact surfaces and by providing contacts to the points of contact of the cell.

Abstract translation: 提供了一种用于创建1T RAM单元的新方法。 施加标准处理以在衬底的表面中产生STI沟槽，在STI沟槽的侧壁中进行N2注入。 产生衬里氧化层，注入的N 2与衬里氧化物相互作用以在STI沟槽的暴露表面上形成SiON。 沉积和抛光STI氧化物，在那里填充STI沟槽。 进行冠图案化以限定电容器区域，冠图案停止在蚀刻停止材料层上，并且所产生的SION并且部分地从STI沟槽去除STI氧化物。 蚀刻停止材料层，暴露的SiON和衬垫氧化物层被去除，暴露硅衬底的表面，STI氧化物的蚀刻层不受该去除的影响。 生长一层SAC氧化物，n阱和p阱注入进行到衬底的表面。 去除SAC氧化物层，生长栅极氧化物，沉积多晶硅并进行图案化和蚀刻，形成电容器的多晶硅栅极材料和多晶硅顶板。 进一步应用标准处理，通过为栅电极提供栅极间隔物和杂质注入，通过对接触表面进行喷淋并且通过提供与电池的接触点的接触来完成1T-RAM单元。

公开(公告)号：US06174802B1

公开(公告)日：2001-01-16

申请号：US09342042

申请日：1999-06-28

Applicant: Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Min-Hsiung Chiang

Inventor： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Min-Hsiung Chiang

IPC: H01L214763

CPC classification number: H01L21/76897

Abstract: A method for forming a self aligned contact without key holes using a two step contact deposition. The process begins by providing a semiconductor structure having conductive structures (such as bit lines) thereover with sidewalls and having a contact area adjacent to the conductive structures. The conductive structures comprise at least one conductive layer with a hard mask thereover. A spacer layer is formed over the hard mask and the substrate structure and anisotropically etched to form sidewall spacers on the sidewalls of the conductive structure. A second dielectric (IPO) layer is formed over the sidewall spacers, the hard mask, and the substrate structure, whereby the second dielectric layer has a keyhole. A contact opening is formed in the second dielectric layer over the contact area. A first contact layer having poor step coverage is formed in the contact openings and over the second dielectric layer, thereby plugging the keyhole without filling it. A second contact layer is formed over the first contact layer.

Abstract translation: 使用两步接触沉积形成无键孔的自对准接触的方法。 该过程开始于提供具有导电结构（例如位线）的半导体结构，其具有侧壁并且具有与导电结构相邻的接触区域。 导电结构包括至少一个具有硬掩模的导电层。 在硬掩模和衬底结构之上形成间隔层，并且各向异性蚀刻以在导电结构的侧壁上形成侧壁间隔物。 在侧壁间隔物，硬掩模和基板结构上方形成第二电介质层（IPO），由此第二介电层具有锁孔。 在接触区域上的第二电介质层中形成接触开口。 在接触开口和第二电介质层上形成具有差的台阶覆盖率的第一接触层，从而在不填充锁孔的情况下封闭钥匙孔。 在第一接触层上形成第二接触层。

公开(公告)号：US6110822A

公开(公告)日：2000-08-29

申请号：US47539

申请日：1998-03-25

Applicant: Kuo-Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Dun-Nian Yaung

Inventor： Kuo-Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Dun-Nian Yaung

IPC: H01L21/20 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/44 ,  H01L21/00 ,  H01L21/84 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/11 ,  H01L21/76838 ,  H01L27/1108 ,  H01L21/2022

Abstract: A method of forming a contact in a thin film transistor with a gate electrode and an interconnect formed on a substrate, in an SRAM device comprises the following steps. Form a gate oxide layer over device. Form a split amorphous silicon layer over gate oxide layer. Form a cap layer over split amorphous silicon layer. Form a contact opening down to interconnect. Form contact metallization in opening on the surface of interconnect either as a blanket titanium layer followed by rapid thermal anneal to form a silicide and stripping unreacted titanium or by selective formation of a tungsten metal silicide in the opening. Strip cap layer from device. Form a second amorphous silicon layer on split silicon layer. Recrystallize silicon layers to form a polysilicon channel layer from amorphous silicon layers. Dope regions of polysilicon channel layer aside from a channel region above gate electrode.

Abstract translation: 在SRAM器件中，在具有形成在衬底上的栅极和互连的薄膜晶体管中形成接触的方法包括以下步骤。 在器件上形成栅氧化层。 在栅极氧化层上形成分裂的非晶硅层。 在分裂的非晶硅层上形成覆盖层。 形成一个联系人开放互连。 在互连表面上开口形成接触金属化，作为覆盖钛层，随后快速热退火以形成硅化物并汽提未反应的钛或通过在开口中选择性形成钨金属硅化物。 从设备剥去盖帽层。 在分裂硅层上形成第二非晶硅层。 重新结晶硅层以形成来自非晶硅层的多晶硅沟道层。 多晶硅沟道层的掺杂区域与栅电极上方的沟道区域不同。

公开(公告)号：US6033985A

公开(公告)日：2000-03-07

申请号：US102374

申请日：1998-06-30

Applicant: Yean-Kuen Fang ,  Kuo-Ching Huang ,  Chung-Yao Chen

Inventor： Yean-Kuen Fang ,  Kuo-Ching Huang ,  Chung-Yao Chen

IPC: H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/8234

CPC classification number: H01L21/76855 ,  H01L21/76843 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1108

Abstract: A contact process interconnects poly-crystal silicon layer, and more particularly, this process dramatically decreases the voltage drop within a poly-crystal silicon layer. The advantages of the process include not only improvement in the interface quality of Poly-Si/SiO2 to decrease the junction damage but also do not increase its process complexity and its mask number during the fabrication of poly-crystal silicon thin-film SRAM to meet high integration requirement in VLSI.

Abstract translation: 接触工艺互连多晶硅层，更具体地说，该工艺显着地降低了多晶硅层内的电压降。 该工艺的优点不仅在于改善Poly-Si / SiO 2的界面质量以减少接合损伤，而且在制造多晶硅薄膜SRAM期间不会增加其工艺复杂性及其掩模编号以满足 VLSI高集成度要求。