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公开(公告)号：US20240363758A1
公开(公告)日：2024-10-31
申请号：US18247554
申请日：2023-02-28
Inventor： Zhifu LI , Guanghui LIU , Chao DAI , Fei AI , Dewei SONG , Zhuang LI
IPC: H01L29/786 , H01L29/417
CPC classification number: H01L29/78603 , H01L29/41733 , H01L29/78633 , H01L29/78696
Abstract: A display panel is provided by embodiments of the present application, a thin film transistor includes: a first gate electrode including a first side slope, a second side slope oppositely arranged, and a top surface; a first gate insulating layer covering the first gate electrode; a semiconductor layer arranged on the first gate insulating layer, wherein the semiconductor layer includes a first end, a second end, and a channel arranged between the first end and the second end, the second end is at least partially on the top surface, the channel is at least partially located on the first side slope.
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公开(公告)号：US20240363640A1
公开(公告)日：2024-10-31
申请号：US18522308
申请日：2023-11-29
Inventor： Fei AI , Dewei SONG , Chengzhi LUO
IPC: H01L27/12
CPC classification number: H01L27/1222 , H01L27/124
Abstract: A display panel and a display device are provided. The display panel includes: an active layer, a gate, and a gate auxiliary structure. The active layer is disposed along a first direction and includes a channel layer. The gate is disposed above the channel layer and a width of the gate along the first direction is equal to a length of the channel layer along the first direction. The gate auxiliary structure is disposed adjacent to the gate. The width of the gate along the first direction is less than 1 micrometer.
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公开(公告)号：US20240152010A1
公开(公告)日：2024-05-09
申请号：US17776384
申请日：2022-04-13
Inventor： Fan GONG , Guanghui LIU , Fei AI , Jiyue SONG , Dewei SONG , Rui HE
IPC: G02F1/1362 , G02F1/1368
CPC classification number: G02F1/136209 , G02F1/136222 , G02F1/1368
Abstract: Embodiments of the present disclosure provide a display panel and a display terminal. The display panel includes at least one ultraviolet sensing transistor and at least one control transistor disposed on a substrate, and a color film substrate including a light blocking unit; wherein the ultraviolet sensing transistor includes an ultraviolet absorbing layer, and an orthographic projection of the light blocking unit on the substrate covers an orthographic projection of the ultraviolet absorbing layer on the substrate. According to the embodiment of the present disclosure, the light blocking unit absorbs or blocks the visible lights to prevent the visible lights from entering into the ultraviolet absorbing layer.
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Patent Agency Ranking
公开(公告)号：US20240055492A1
公开(公告)日：2024-02-15
申请号：US17910256
申请日：2022-08-30
Inventor： Fei Al , Dewei SONG
IPC: H01L29/417 , H01L29/786
CPC classification number: H01L29/41733 , H01L29/78603 , H01L29/78624 , H01L29/78642 , H01L27/3262
Abstract: The present disclosure provides a vertical inverter and a semiconductor device including the vertical inverter, and the vertical inverter includes an insulation substrate, a first thin film transistor, and a second thin film transistor. By a layered arrangement of the first and second thin film transistors of the vertical inverter, more thin film transistors can be arranged within the limited space, so that the integration degree of the thin film transistors in the semiconductor device can be improved.
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公开(公告)号：US20240021765A1
公开(公告)日：2024-01-18
申请号：US17414019
申请日：2021-06-04
Inventor： Jiyue SONG , Fei AI , Dewei SONG
CPC classification number: H01L33/62 , H01L33/0012 , G06V40/13 , H01L2933/0016 , H01L2933/0025 , H01L2933/0033
Abstract: In an array substrate of the present invention, only two insulating layers are arranged on a planarization layer. Compared with conventional techniques that require at least four insulating layers arranged on the planarization layer, a number of the insulating layers arranged on the planarization layer is reduced. Therefore, a number of photomasks is reduced in a manufacturing process of the array substrate, and the manufacturing process is simplified. The present invention also provides a manufacturing method of the array substrate, and a display panel.
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公开(公告)号：US20230176410A1
公开(公告)日：2023-06-08
申请号：US16963787
申请日：2020-06-23
Inventor： Dewei SONG , Fei AI
IPC: G02F1/1333 , G02F1/1368 , H01L27/12
CPC classification number: G02F1/133354 , G02F1/1368 , H01L27/1248
Abstract: The present application provides a display panel and a display device. The display panel includes an array substrate, a color filter substrate, and a colloid layer. The array substrate includes a thin film transistor layer and a passivation layer. The passivation layer includes at least one first connection element. The color filter substrate is disposed opposite to the array substrate. The colloid layer is arranged between the passivation layer and the color filter substrate, the colloid layer is connected to the first connection element, and the colloid layer and the first connection element couple the array substrate to the color filter substrate.
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公开(公告)号：US20230163136A1
公开(公告)日：2023-05-25
申请号：US16966119
申请日：2020-04-20
Inventor： Juncheng XIAO , Yong XU , Fei AI , Dewei SONG
IPC: H01L27/12
CPC classification number: H01L27/1225 , H01L27/1288 , H01L27/1285
Abstract: A display panel, an array substrate, and a manufacturing method thereof, wherein the array substrate includes a thin film transistor device, and an interface layer, a first transparent conductive layer, a passivation layer, and a second transparent conductive layer which are formed on the thin film transistor device in sequence. By replacing a planarization layer in the prior art with the interface layer, performing a gate re-etching process, and perforating the interface layer and the passivation layer to simultaneously form a deep via and a shallow via, a number of photomasks required to form the array substrate is reduced to 8. It effectively reduces costs of production materials and costs of photomasks.
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公开(公告)号：US20210408080A1
公开(公告)日：2021-12-30
申请号：US16757175
申请日：2019-12-12
Inventor： Fei AI , Dewei SONG
IPC: H01L27/12 , G02F1/1368 , G02F1/1343 , G02F1/136
Abstract: The invention provides a thin film transistor (TFT) array substrate, a manufacturing method thereof, and a display panel. The TFT array substrate includes a substrate. A buffer layer and a TFT functional layer are sequentially disposed on the substrate. The TFT functional layer includes an active layer (Active), a gate insulating layer (GI), a gate layer (GE), an interlayer insulating layer (ILD), and a source-drain layer (SD) that are sequentially disposed on the buffer layer. An inorganic insulating layer is disposed on the source-drain layer, and a backside indium tin oxide (BITO) layer, a passivation layer (PV), and a top indium tin oxide (TITO) layer are sequentially disposed on the inorganic insulating layer. The invention provides the TFT array substrate. The TFT array substrate adopts a new functional layer structure design, which can effectively reduce production cost and cycle time of the TFT array substrate.
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