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21.发明授权公开(公告)号：US08742512B2
公开(公告)日：2014-06-03
申请号：US13609866
申请日：2012-09-11
申请人： Takeshi Kishida
发明人： Takeshi Kishida
IPC分类号： H01L21/70
CPC分类号： H01L27/092 , H01L21/82345 , H01L21/823842 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： A semiconductor device according to the invention includes: a first region on a semiconductor substrate, in which a first transistor is formed, the first transistor including first gate insulating film 4 containing a high dielectric constant material and first metal gate electrode 5 formed on first gate insulating film 4; a second region adjacent to the first region on the semiconductor substrate, in which a second transistor is formed, the second transistor including second gate insulating film 4 and second metal gate electrode 12 formed on the second gate insulating film, a layered structure of electrode materials of the second transistor being different from a layered structure of electrode materials of the first transistor; and a first and a second line, the lines being of different potentials, wherein a border between the first and the second region overlaps with at most only the first or the second line.
摘要翻译： 根据本发明的半导体器件包括：半导体衬底上形成第一晶体管的第一区域，第一晶体管包括第一栅绝缘膜4，第一栅极绝缘膜4包含高介电常数材料，第一金属栅电极5形成在第一栅极上 绝缘膜4; 与半导体衬底上的第一区域相邻的第二区域，其中形成第二晶体管，所述第二晶体管包括形成在第二栅极绝缘膜上的第二栅极绝缘膜4和第二金属栅电极12，电极材料的层叠结构 所述第二晶体管与所述第一晶体管的电极材料的分层结构不同; 以及第一和第二线，所述线具有不同的电位，其中所述第一和第二区之间的边界与所述第一或第二线最多重叠。
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公开(公告)号：US20060244866A1
公开(公告)日：2006-11-02
申请号：US11377004
申请日：2006-03-16
申请人： Takeshi Kishida
发明人： Takeshi Kishida
CPC分类号： G06K9/6218 , G06K9/00771 , G06T7/231 , G06T2207/10016 , G06T2207/30232
摘要： A moving object detection device accurately detects moving objects. The device includes a motion vector calculation section calculating motion vectors from an input image; a motion vector removal section removing a motion vector having high randomness from the calculated motion vectors; a motion vector accumulation section temporally accumulating each motion vector not removed by the motion vector removal section, and calculating an accumulated number of occurrences and an accumulated value of each motion vector; and a moving object detection section determining, based on the calculated accumulated value and calculated accumulated number of occurrences of each motion vector, whether each motion vector corresponds to a moving object.
摘要翻译： 运动物体检测装置精确地检测运动物体。 该装置包括运动矢量计算部分，用于从输入图像计算运动矢量; 运动矢量去除部分，从计算出的运动矢量中去除具有高随机性的运动矢量; 运动矢量累积部分，其时间上累积由运动矢量除去部分未被去除的每个运动矢量，并且计算累积的出现次数和每个运动矢量的累积值; 以及运动对象检测部，其基于计算出的累积值和计算出的每个运动矢量的累计出现次数来确定每个运动矢量是否对应于运动对象。
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公开(公告)号：US06744143B1
公开(公告)日：2004-06-01
申请号：US09620718
申请日：2000-07-20
申请人： Jiro Matsufusa , Tomoharu Mametani , Takeshi Kishida , Yoji Nakata , Yukihiro Nagai , Hiroaki Nishimura , Akinori Kinugasa , Shigenori Kido
发明人： Jiro Matsufusa , Tomoharu Mametani , Takeshi Kishida , Yoji Nakata , Yukihiro Nagai , Hiroaki Nishimura , Akinori Kinugasa , Shigenori Kido
IPC分类号： H01L23544
CPC分类号： G03F7/70633 , H01L21/31612 , H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a test mark comprising: a semiconductor substrate; a first TEOS layer formed on the semiconductor substrate; a second TEOS layer formed on the first TEOS layer and having a fluidity lower than that of the first TEOS layer at an elevated temperature; a recess formed in the first and second TEOS layers and exposing the surface of the semiconductor substrate, wherein the horizontal cross section of the recess is substantially rectangular in configuration; and a metal layer formed between the first and second TEOS layers and opposing to the corner of the recess.
摘要翻译： 一种具有测试标记的半导体器件，包括：半导体衬底; 形成在所述半导体衬底上的第一TEOS层; 形成在第一TEOS层上并且在升高的温度下具有低于第一TEOS层的流动性的第二TEOS层; 形成在所述第一和第二TEOS层中并且暴露所述半导体衬底的表面的凹部，其中所述凹部的水平横截面基本上为矩形; 以及形成在第一和第二TEOS层之间并且与凹部的拐角相对的金属层。
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公开(公告)号：US06673671B1
公开(公告)日：2004-01-06
申请号：US09722479
申请日：2000-11-28
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817
摘要： There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.
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25.发明授权公开(公告)号：US06400022B1
公开(公告)日：2002-06-04
申请号：US09907689
申请日：2001-07-19
申请人： Takeshi Kishida , Shigenori Kido
发明人： Takeshi Kishida , Shigenori Kido
IPC分类号： H01L2840
CPC分类号： H01L21/76838 , H01L27/10852 , H01L28/75 , H01L28/91
摘要： A semiconductor device with a high reliability is provided. The semiconductor device includes a silicon substrate, titanium nitride films and an interlayer insulating film. A first opening is formed in the titanium nitride film. A second opening having a diameter different from that of the first opening is formed in the second titanium nitride film. A contact hole is formed in the interlayer insulating film. A titanium film, a titanium nitride film, a plug layer and an interconnect layer are formed so as to be electrically connected to the titanium nitride films through the first and second openings.
摘要翻译： 提供了具有高可靠性的半导体器件。 该半导体器件包括硅衬底，氮化钛膜和层间绝缘膜。 在氮化钛膜中形成第一开口。 在第二氮化钛膜中形成具有与第一开口的直径不同的直径的第二开口。 在层间绝缘膜中形成接触孔。 形成钛膜，氮化钛膜，插塞层和互连层，以通过第一和第二开口与氮化钛膜电连接。
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公开(公告)号：US06251741B1
公开(公告)日：2001-06-26
申请号：US09219786
申请日：1998-12-23
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817
摘要： There is described the manufacture of a semiconductor device having a storage node or high-yield manufacture of a compact memory IC. The present invention provides a method of manufacturing a semiconductor device including a basic dielectric layer formation step for forming a basic dielectric layer from a first dielectric material, a stopper film formation step for forming on the basic dielectric layer an etch stopper film from a second dielectric material differing from the first dielectric film, a sacrificial dielectric layer formation step for forming on the etch stopper film a sacrificial dielectric layer from the first dielectric material, a space formation step for forming a storage node formation space by removal of a predetermined area from the sacrificial dielectric layer until the etch stopper film becomes exposed, a storage node formation step for forming in the storage node formation space a storage node from a capacitive material, and a sacrificial dielectric layer removal step for removing the sacrificial dielectric layer surrounding the storage node by means of an etching operation suitable for removal of the first dielectric material.
摘要翻译： 描述了具有存储节点或紧凑型存储器IC的高产量制造的半导体器件的制造。 本发明提供一种制造半导体器件的方法，该半导体器件包括用于从第一介电材料形成基本电介质层的基本电介质层形成步骤，用于在基本电介质层上形成来自第二电介质的蚀刻停止膜的阻挡膜形成步骤 与第一介电膜不同的材料;牺牲介电层形成步骤，用于在蚀刻停止膜上形成来自第一介电材料的牺牲介电层;空间形成步骤，用于通过从第一电介质膜去除预定区域形成存储节点形成空间; 牺牲电介质层，直到蚀刻停止膜露出，存储节点形成步骤，用于在存储节点形成空间中形成存储节点与电容材料;以及牺牲介电层去除步骤，用于通过以下步骤去除存储节点周围的牺牲介电层： 蚀刻操作的手段适合于去除 l的第一介电材料。
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公开(公告)号：US20090146273A1
公开(公告)日：2009-06-11
申请号：US11997700
申请日：2006-07-28
IPC分类号： H01L23/495
CPC分类号： H01L24/06 , H01L23/50 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06153 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48599 , H01L2224/49113 , H01L2224/4917 , H01L2224/49171 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/3011 , H01L2224/78 , H01L2924/00
摘要： There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions.In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is made different from an arrangement order of the function terminals on the external package.
摘要翻译： 提供了一种半导体器件，其采用连接到LSI上的外部封装的焊盘的布局，其中焊盘布置移位的之字形焊盘布局，这可以避免导线短路的发生，芯片的增加 由于避免短路，由于IO单元间隔的减少而导致的电源传播或GND噪声，以及由于焊盘位置的位移引起的信号传输延迟差异。 在半导体装置中，与外部封装上的功能端子连接的半导体元件上的多个焊盘沿着半导体元件的周边配置成两列，半导体元件上的多个焊盘的排列顺序与 功能端子在外部封装上的布置顺序。
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公开(公告)号：US20070272963A1
公开(公告)日：2007-11-29
申请号：US11807494
申请日：2007-05-29
申请人： Takeshi Kishida
发明人： Takeshi Kishida
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10852 , H01L28/91
摘要： A semiconductor device having in a deep hole formed in a first interlayer insulating film a memory cell region that comprises a plurality of capacitors having a lower electrode 229 composed of a crown structure having an outside face and inner face, a first upper electrode 231 facing the outside face of the lower electrode, and a dielectric and a second upper electrode extending from the inner face of the lower electrode to the surface of a first interlayer insulating film other than the deep hole; wherein the first upper electrode is connected to the second upper electrode by connecting a first upper electrode 227 formed on the inner wall of the deep hole to the wiring 241a via a conductor film 224 and a conductor plug 236a, and connecting a second upper electrode 231 to be a plate to a wiring 241a via a conductor plug 239a.
摘要翻译： 一种在第一层间绝缘膜中形成有深孔的半导体器件，存储单元区域包括具有由具有外表面和内表面的表冠结构构成的下电极229的多个电容器，面向 下电极的外表面以及从下电极的内表面延伸到除了深孔以外的第一层间绝缘膜的表面的电介质和第二上电极; 其中，所述第一上部电极通过经由导体膜224和导体插塞236a将形成在深孔的内壁上的第一上部电极227与布线241a连接而与第二上部电极连接，并且将第二上部电极 电极231经由导体插塞239a成为布线241a的板。
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29.发明授权Method of fabricating semiconductor device comprising superposition inspection step 失效制造半导体器件的方法，包括叠加检查步骤公开(公告)号：US06775920B2
公开(公告)日：2004-08-17
申请号：US10437911
申请日：2003-05-15
申请人： Takeshi Kishida , Shigenori Kido
发明人： Takeshi Kishida , Shigenori Kido
IPC分类号： G01D2100
CPC分类号： H01L23/544 , G03F7/70633 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A photolithography step is carried out for exposing/etching a resist film in an etching step. Thereafter a superposition inspection step employing a superposed layer superposition mark and a resist film superposition mark is carried out with a superposition inspection apparatus. In this step, an applied mask confirmation step is simultaneously carried out with the superposition inspection apparatus. Thus, it is possible to provide a method of fabricating a semiconductor device including a superposition inspection step, capable of efficiently confirming an applied mask and improving the fabrication yield for the semiconductor device.
摘要翻译： 在蚀刻步骤中进行曝光/蚀刻抗蚀剂膜的光刻步骤。 此后，使用重叠检查装置进行使用叠加层叠加标记和抗蚀剂膜叠加标记的叠加检查步骤。 在该步骤中，与叠加检查装置同时进行应用的掩模确认步骤。 因此，可以提供一种制造包括叠加检查步骤的半导体器件的方法，其能够有效地确认所施加的掩模并且提高半导体器件的制造成品率。
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