公开(公告)号：US20180068050A1

公开(公告)日：2018-03-08

申请号：US15258932

申请日：2016-09-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng LIN ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Ru-Gun LIU ,  Shih-Wei PENG ,  Wei-Chen CHIEN

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072

Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.

公开(公告)号：US20170317089A1

公开(公告)日：2017-11-02

申请号：US15362002

申请日：2016-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Charles Chew-Yuen YOUNG ,  Chin-Yuan TSENG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Ru-Gun LIU ,  Wei-Liang LIN ,  L. C. CHOU

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/308

CPC classification number: H01L27/1104 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886

Abstract: A method, of manufacturing fins for a semiconductor device which includes Fin-FETs, includes: forming a structure including a semiconductor substrate and capped semiconductor fins, the capped semiconductor fins being organized into at least first and second sets, with each member of the first set having a first cap with a first etch sensitivity, and each member of the second set having a second cap with a second etch, the second etch sensitivity being different than the first etch sensitivity; removing selected members of the first set and selected members of the second set from the structure.

公开(公告)号：US20250063823A1

公开(公告)日：2025-02-20

申请号：US18936851

申请日：2024-11-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG

IPC: H01L27/02 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit includes a driver cell and at least one transmission cell. The driver cell includes a first active area and a second active area, and a first conductive line coupled to the first active area and the second active area on a back side of the integrated circuit. The at least one transmission cell having a second cell height includes a third active area and a fourth active area, a second conductive line coupled to the third active area and the fourth active area on the back side of the integrated circuit, and a conductor coupled to the third active area and the fourth active area. The integrated circuit further includes a third conductive line coupled between the first conductive line and the second conductive line on the back side to transmit a signal between the driver cell and the at least one transmission cell.

公开(公告)号：US20250022801A1

公开(公告)日：2025-01-16

申请号：US18897494

申请日：2024-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Te-Hsin CHIU ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092

Abstract: An integrated circuit includes a first and second power rail extending in a first direction and being on a first level of a back-side of a substrate, a first and second active region and a first conductive line. The first power rail is configured to supply a first supply voltage. The second power rail is configured to supply a second supply voltage. The first and second active region extend in the first direction, and are on a second level of a front-side of the substrate opposite from the back-side. The first active region is overlapped by the first power rail. The second active region is overlapped by the second power rail. The first conductive line extends in the second direction, is on a third level of the back-side of the substrate, and overlaps the first and second active region.

公开(公告)号：US20240395793A1

公开(公告)日：2024-11-28

申请号：US18791032

申请日：2024-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG

IPC: H01L27/02 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit includes a driver cell and at least one transmission cell. The driver cell includes a first active area and a second active area, and a first conductive line coupled to the first active area and the second active area on a back side of the integrated circuit. The at least one transmission cell having a second cell height includes a third active area and a fourth active area, a second conductive line coupled to the third active area and the fourth active area on the back side of the integrated circuit, and a conductor coupled to the third active area and the fourth active area. The integrated circuit further includes a third conductive line coupled between the first conductive line and the second conductive line on the back side to transmit a signal between the driver cell and the at least one transmission cell.

公开(公告)号：US20240055029A1

公开(公告)日：2024-02-15

申请号：US18447788

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Wei PENG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO

IPC: G11C5/14 ,  G11C5/06 ,  H01L23/538 ,  H01L23/50

CPC classification number: G11C5/14 ,  G11C5/06 ,  H01L23/5386 ,  H01L23/50

Abstract: Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.

公开(公告)号：US20220392885A1

公开(公告)日：2022-12-08

申请号：US17818053

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Wei-Cheng LIN

IPC: H01L27/02 ,  H01L27/12 ,  H01L21/84 ,  H03K3/037

Abstract: An integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. The first active area is arranged to overlap the first pair of power rails. The first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias.

公开(公告)号：US20220328397A1

公开(公告)日：2022-10-13

申请号：US17846650

申请日：2022-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Te-Hsin CHIU ,  Wei-An LAI ,  Meng-Hung SHEN ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG ,  Kam-Tou SIO

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: A method for fabricating a semiconductor structure includes depositing a first insulation material over a substrate, wherein the substrate includes an active region. The method further includes etching the first insulation material to define a first recess extending along a first direction at a first level of the first insulation material. The method further includes depositing a second insulation material lining with a sidewall of the first recess. The method further includes depositing a first metal line in the first recess.

公开(公告)号：US20220157714A1

公开(公告)日：2022-05-19

申请号：US17590439

申请日：2022-02-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: A method including depositing a first dielectric layer over a first conductive line. The method further includes forming a first opening in the first dielectric layer. The method further includes filling the first opening with a first conductive material to define a second conductive line. The method further includes depositing a second dielectric layer over the first dielectric layer. The method further includes forming a second opening in the second dielectric layer. The method further includes filling the second opening with a second conductive material to define a third conductive line. The method further includes forming a supervia opening in the first dielectric layer and the second dielectric layer. The method further includes filling the supervia opening with a third conductive material to define a supervia, wherein the supervia directly connects to the first conductive line and the third conductive line.

公开(公告)号：US20220130817A1

公开(公告)日：2022-04-28

申请号：US17081807

申请日：2020-10-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Wei-Cheng LIN

IPC: H01L27/02 ,  H01L27/12 ,  H01L21/84 ,  H03K3/037

Abstract: An integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. The first active area is arranged to overlap the first pair of power rails. The first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias.