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    Inductor structure with magnetic material
    21.
    发明授权
    Inductor structure with magnetic material 有权
    具有磁性材料的电感结构

    公开(公告)号：US09048128B2

    公开(公告)日：2015-06-02

    申请号：US14044979

    申请日：2013-10-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

    Inventor： Yuan-Tai Tseng ,  Ming-Chyi Liu ,  Chung-Yen Chou ,  Chia-Shiung Tsai

    IPC: H01L29/00 ,  H01L49/02

    CPC classification number: H01F27/2804 ,  H01F1/0306 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/24 ,  H01F2017/0066 ,  H01F2027/2809 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of mechanisms of forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure includes a first metal layer formed in the first dielectric layer and a second dielectric layer over the first metal layer. The inductor structure further includes a magnetic layer formed over the first dielectric layer, and the magnetic layer has a top surface, a bottom surface and sidewall surfaces between the top surface and the bottom surface, and the sidewall surfaces have at least two intersection points.

    Abstract translation: 提供了形成电感器结构的机构的实施例。 电感器结构包括衬底和形成在衬底上的第一介电层。 电感器结构包括形成在第一电介质层中的第一金属层和在第一金属层上的第二电介质层。 电感器结构还包括形成在第一介电层上的磁性层，并且磁性层具有顶表面，底表面和顶表面与底表面之间的侧壁表面，并且侧壁表面具有至少两个交点。

    Passivation Structure With Increased Thickness for Metal Pads
    24.
    发明申请
    Passivation Structure With Increased Thickness for Metal Pads 有权

    公开(公告)号：US20220384331A1

    公开(公告)日：2022-12-01

    申请号：US17818736

    申请日：2022-08-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Shu Huang ,  Ming-Chyi Liu

    IPC: H01L23/498 ,  H01L23/495 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31

    Abstract: A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

    Double channel memory device
    25.
    发明授权
    Double channel memory device 有权

    公开(公告)号：US11158648B2

    公开(公告)日：2021-10-26

    申请号：US16354001

    申请日：2019-03-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hung-Shu Huang ,  Ming-Chyi Liu

    IPC: H01L29/792 ,  H01L27/1157 ,  H01L21/311 ,  H01L21/033 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

    Abstract: A semiconductor device includes a substrate, a fin structure, an insulating layer, a select gate, a memory gate, and a charge trapping layer. The fin structure includes a first portion and a second extend from the substrate. Each of the first portion and the second portion includes a first sidewall and a second sidewall, and the second sidewalls are between the first sidewalls. The insulating layer is disposed between the second sidewalls of the first and second portions. The select gate and the memory gate extend across the fin structure and the insulating layer. The charge trapping layer is disposed between the memory gate and the select gate, between the memory gate and the insulating layer, and between the memory gate and the fin structure, and the second sidewalls of the first and second portions are free from in contact with the charge trapping layer.

    Memory device and manufacturing method thereof
    27.
    发明授权
    Memory device and manufacturing method thereof 有权

    公开(公告)号：US10784278B2

    公开(公告)日：2020-09-22

    申请号：US16171353

    申请日：2018-10-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yong-Sheng Huang ,  Ming-Chyi Liu

    IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/28 ,  H01L23/528

    Abstract: A memory device and a manufacturing method are provided. The memory device includes a plurality of memory cells stacked on a substrate. The memory cell includes two conductive patterns, a channel pillar, a gate pattern and a charge storage layer. The two conductive patterns are stacked on the substrate. The channel pillar extends between the two conductive patterns along a stacking direction of the two conductive patterns, and is electrically connected with the two conductive patterns. The gate pattern is disposed between the two conductive patterns and located at a sidewall of the channel pillar. The charge storage layer is disposed between the gate pattern and the channel pillar.

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    28.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200035701A1

    公开(公告)日：2020-01-30

    申请号：US16171353

    申请日：2018-10-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yong-Sheng Huang ,  Ming-Chyi Liu

    IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/28 ,  H01L23/528

    Abstract: A memory device and a manufacturing method are provided. The memory device includes a plurality of memory cells stacked on a substrate. The memory cell includes two conductive patterns, a channel pillar, a gate pattern and a charge storage layer. The two conductive patterns are stacked on the substrate. The channel pillar extends between the two conductive patterns along a stacking direction of the two conductive patterns, and is electrically connected with the two conductive patterns. The gate pattern is disposed between the two conductive patterns and located at a sidewall of the channel pillar. The charge storage layer is disposed between the gate pattern and the channel pillar.

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