公开(公告)号：US20230200264A1

公开(公告)日：2023-06-22

申请号：US18172762

申请日：2023-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Miao Liu ,  Bwo-Ning Chen ,  Kei-Wei Chen

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/231 ,  H10N70/253

Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

公开(公告)号：US11637021B2

公开(公告)日：2023-04-25

申请号：US17323951

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Sheng Lin ,  Chi-Jen Liu ,  Chi-Hsiang Shen ,  Te-Ming Kung ,  Chun-Wei Hsu ,  Chia-Wei Ho ,  Yang-Chun Cheng ,  William Weilun Hong ,  Liang-Guang Chen ,  Kei-Wei Chen

IPC: H01L21/321 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  C09G1/02

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

公开(公告)号：US11532514B2

公开(公告)日：2022-12-20

申请号：US17207227

申请日：2021-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Tang-Kuei Chang ,  Chia Hsuan Lee ,  Jian-Ci Lin

IPC: H01L21/768 ,  H01L21/321 ,  C09G1/04 ,  H01L23/532 ,  H01L23/535

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.

公开(公告)号：US20220359277A1

公开(公告)日：2022-11-10

申请号：US17815407

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Cheng Chen ,  Huicheng Chang ,  Fu-Ming Huang ,  Kei-Wei Chen ,  Liang-Yin Chen ,  Tang-Kuei Chang ,  Yee-Chia Yeo ,  Wei-Wei Liang ,  Ji Cui

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/535 ,  H01L23/532

Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

公开(公告)号：US11450565B2

公开(公告)日：2022-09-20

申请号：US16997616

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Cheng Chen ,  Huicheng Chang ,  Fu-Ming Huang ,  Kei-Wei Chen ,  Liang-Yin Chen ,  Tang-Kuei Chang ,  Yee-Chia Yeo ,  Wei-Wei Liang ,  Ji Cui

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/535 ,  H01L23/532

Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

公开(公告)号：US20210399221A1

公开(公告)日：2021-12-23

申请号：US17463790

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Miao Liu ,  Bwo-Ning Chen ,  Kei-Wei Chen

IPC: H01L45/00

Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

公开(公告)号：US20210327720A1

公开(公告)日：2021-10-21

申请号：US17364313

申请日：2021-06-30

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Yen-Ting Chen ,  Chun-Hao Kung ,  Tung-Kai Chen ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: H01L21/321 ,  C09K3/14 ,  B24B57/02 ,  B24B37/04 ,  B01F13/08

Abstract: A chemical-mechanical polishing (CMP) system includes a head, a polishing pad, and a magnetic system. The slurry used in the CMP process contains magnetizable abrasives. Application and control of a magnetic field, by the magnetic system, allows precise control over how the magnetizable abrasives in the slurry may be drawn toward the wafer or toward the polishing pad.

公开(公告)号：US11037799B2

公开(公告)日：2021-06-15

申请号：US16400620

申请日：2019-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Sheng Lin ,  Chi-Jen Liu ,  Kei-Wei Chen ,  Liang-Guang Chen ,  Te-Ming Kung ,  William Weilun Hong ,  Chi-Hsiang Shen ,  Chia-Wei Ho ,  Chun-Wei Hsu ,  Yang-Chun Cheng

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/321 ,  H01L21/768 ,  C09G1/02

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

公开(公告)号：US10947414B2

公开(公告)日：2021-03-16

申请号：US16503255

申请日：2019-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang-I Chih ,  Chih-Chieh Chang ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: C09G1/02 ,  B24B37/20 ,  C09G1/04 ,  H01L21/306 ,  H01L21/321

Abstract: A polishing composition for a chemical mechanical polishing process includes abrasive particles, at least one chemical additive, and a non-aqueous solvent.

公开(公告)号：US10665717B2

公开(公告)日：2020-05-26

申请号：US16112766

申请日：2018-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L21/285 ,  H01L21/768

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.