公开(公告)号：US20210242078A1

公开(公告)日：2021-08-05

申请号：US16943815

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hwei-Jay CHU ,  Chieh-Han WU ,  Cheng-Hsiung TSAI ,  Chih-Wei LU ,  Chung-Ju LEE

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522

Abstract: A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.

公开(公告)号：US20200343180A1

公开(公告)日：2020-10-29

申请号：US16926942

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Yung-Hsu WU ,  Chung-Ju LEE

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a conductive layer over a semiconductor substrate and forming a sacrificial layer over the conductive layer. The method also includes partially removing the sacrificial layer to form a first dummy element. The method further includes etching the conductive layer with the first dummy element as an etching mask to form a conductive line. In addition, the method includes partially removing the first dummy element to form a second dummy element over the conductive line. The method also includes forming a dielectric layer to surround the conductive line and the second dummy element and removing the second dummy element to form a via hole exposing the conductive line. The method further includes forming a conductive via in the via hole.

公开(公告)号：US20200243754A1

公开(公告)日：2020-07-30

申请号：US16847447

申请日：2020-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen TIEN ,  Wei-Hao LIAO ,  Pin-Ren DAI ,  Chih-Wei LU ,  Chung-Ju LEE

IPC: H01L43/08 ,  H01L23/522 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L43/12

Abstract: A semiconductor device includes a semiconductor substrate, a bottom electrode, a magnetic tunneling junction (MTJ), a top electrode, and a residue. The bottom electrode is disposed over the semiconductor substrate. The MTJ is disposed over the bottom electrode. The top electrode is disposed over the MTJ layer. Sidewalls of the bottom electrode, the MTJ, and the top electrode are vertically aligned with each other. The residue of the MTJ is located on the sidewall of the bottom electrode.

公开(公告)号：US20200066975A1

公开(公告)日：2020-02-27

申请号：US16664813

申请日：2019-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei LU ,  Hsi-Wen TIEN ,  Wei-Hao LIAO ,  David DAI ,  Chung-Ju LEE

IPC: H01L43/12 ,  H01L45/00 ,  H01L43/08 ,  H01L27/24 ,  H01L43/02 ,  H01L27/22

Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a first spacer, and a metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The first spacer is disposed along a sidewall of the resistance switching element. The metal-containing compound layer is disposed along a sidewall of the first spacer, in which the first spacer is between the metal-containing compound layer and the resistance switching element.

公开(公告)号：US20190164781A1

公开(公告)日：2019-05-30

申请号：US15828077

申请日：2017-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen TIEN ,  Wei-Hao LIAO ,  Chih-Wei LU ,  Pin-Ren DAI ,  Chung-Ju LEE

IPC: H01L21/48 ,  H01L23/532 ,  H01L23/522

Abstract: A method for forming an interconnect structure is provided. The method includes: forming a dielectric layer on a substrate, and forming an opening in the dielectric layer; forming a first metal layer, a second metal layer, and a third metal layer sequentially over the dielectric layer. The opening of the dielectric layer is filled with the first metal layer to form a conductive via. The method also includes: performing one or multiple etch operation to etch the first metal layer, the second metal layer, and the third metal layer, so as to form a metal line corresponding to the first metal layer, an intermediate metal layer corresponding to the second metal layer, and a metal pillar corresponding to the third metal layer. In particular, the width of the metal line is greater than the width of the metal pillar.

公开(公告)号：US20190148623A1

公开(公告)日：2019-05-16

申请号：US15811405

申请日：2017-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao LIAO ,  Chih-Wei LU ,  Hsi-Wen TIEN ,  Pin-Ren DAI ,  Chung-Ju LEE

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: A memory device includes an MTJ structure and a first metal residue. The MTJ structure includes a top surface having a first width, a bottom surface having a second width greater than the first width, and a stepped sidewall structure between the top surface and the bottom surface. The stepped sidewall structure includes a first sidewall, a second sidewall, and an intermediary surface connecting the first sidewall to the second sidewall. The first metal residue is in contact with the first sidewall and not in contact with the second sidewall.

公开(公告)号：US20190088863A1

公开(公告)日：2019-03-21

申请号：US15706709

申请日：2017-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei LU ,  Hsi-Wen TIEN ,  Wei-Hao LIAO ,  David DAI ,  Chung-Ju LEE

IPC: H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/249 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16

Abstract: A method for manufacturing a memory device is provided. The method includes forming a stack over a first portion of a bottom electrode layer, in which the stack comprises a resistance switching element and a top electrode over the resistance switching element; forming a first spacer around the resistance switching element; forming a penetration barrier layer around the resistance switching element; and removing a second portion of the bottom electrode layer using an etch operation, in which the penetration barrier layer has higher resistance to penetration of an etchant used in the etch operation than that of the first spacer.