公开(公告)号：US20180069006A1

公开(公告)日：2018-03-08

申请号：US15452203

申请日：2017-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung Kim ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7845

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.