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    SYSTEMS AND METHODS FOR A REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) USING A DECODER IN CACHE COHERENT INTERCONNECT STORAGE DEVICES
    22.
    发明公开
    SYSTEMS AND METHODS FOR A REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) USING A DECODER IN CACHE COHERENT INTERCONNECT STORAGE DEVICES 审中-公开

    公开(公告)号：US20230409196A1

    公开(公告)日：2023-12-21

    申请号：US17885520

    申请日：2022-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tong ZHANG ,  Heekwon PARK ,  Rekha PITCHUMANI ,  Yang Seok KI

    IPC: G06F3/06

    CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0689

    Abstract: A system is disclosed. The system may include a processor that may issue a byte level protocol request including a byte address. The system may also include a first storage device and a second storage device. The first storage device and the second storage device may support a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. The first storage device and the second storage device are included in a redundant array of independent disks (RAID). The first storage device may include a first address range, and the second storage device may include a second address range. The second storage device may provide a RAID address range associated with the first address range and the second address range. A decoder associated with the second storage device may be configured to receive the request from the processor. The decoder may determine that the byte address in the RAID address range is associated with a target address range.

    FPGA ACCELERATION SYSTEM FOR MSR CODES
    23.
    发明公开
    FPGA ACCELERATION SYSTEM FOR MSR CODES 审中-公开

    公开(公告)号：US20230367675A1

    公开(公告)日：2023-11-16

    申请号：US18223019

    申请日：2023-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mian QIN ,  Joo Hwan LEE ,  Rekha PITCHUMANI ,  Yang Seok KI

    IPC: G06F11/10 ,  G06F13/28

    CPC classification number: G06F11/1076 ,  G06F13/28

    Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

    SYSTEM AND METHOD FOR IN-SSD DATA PROCESSING ENGINE SELECTION BASED ON STREAM IDS
    25.
    发明申请
    SYSTEM AND METHOD FOR IN-SSD DATA PROCESSING ENGINE SELECTION BASED ON STREAM IDS 有权

    公开(公告)号：US20230079467A1

    公开(公告)日：2023-03-16

    申请号：US18055371

    申请日：2022-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jing YANG ,  Jingpei YANG ,  Rekha PITCHUMANI

    IPC: G06F3/06

    Abstract: A multi-stream memory system includes an in-device data processor including a first data processing engine and a second data processing engine, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform: identifying a stream ID of an input stream, identifying the first data processing engine as being associated with the stream ID based on a stream assignment table, and applying the first data processing engine to the input stream to generate processed data.

    SYSTEMS, METHODS, AND DEVICES FOR BIAS MODE MANAGEMENT IN MEMORY SYSTEMS
    26.
    发明申请
    SYSTEMS, METHODS, AND DEVICES FOR BIAS MODE MANAGEMENT IN MEMORY SYSTEMS 有权

    公开(公告)号：US20220405207A1

    公开(公告)日：2022-12-22

    申请号：US17500927

    申请日：2021-10-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Armin HAJ ABOUTALEBI ,  Rekha PITCHUMANI ,  Zongwang LI ,  Marie Mai NGUYEN

    IPC: G06F12/0882 ,  G06F12/02 ,  G06F13/16 ,  G06K9/62 ,  G06N20/00

    Abstract: A method for managing a memory system may include monitoring one or more accesses of a page of memory, determining, based on the monitoring, an access pattern of the page of memory, and selecting, based on the access pattern, a coherency bias for the page of memory. The monitoring may include maintaining an indication of the one or more accesses. The determining may include comparing the indication to a threshold. Maintaining the indication may include changing the indication in a first manner based on an access of the page of memory by a first apparatus. Maintaining the indication may include changing the indication in a second manner based on an access of the page of memory by a second apparatus. The first manner may counteract the second manner.

    SYSTEMS, METHODS, AND APPARATUS FOR PAGE MIGRATION IN MEMORY SYSTEMS
    27.
    发明申请
    SYSTEMS, METHODS, AND APPARATUS FOR PAGE MIGRATION IN MEMORY SYSTEMS 有权

    公开(公告)号：US20220382478A1

    公开(公告)日：2022-12-01

    申请号：US17393399

    申请日：2021-08-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Heekwon PARK ,  Rekha PITCHUMANI

    IPC: G06F3/06

    Abstract: A method for managing a memory system may include monitoring a page of a first memory of a first type, determine a usage of the page based on the monitoring, and migrating the page to a second memory of a second type based on the usage of the page. Monitoring the page may include monitoring a mapping of the page. Monitoring the mapping of the page may include monitoring a mapping of the page from a logical address to a physical address. Determining the usage of the page may include determining an update frequency of the page. Determining the usage of the page may include comparing the update frequency of the page to a threshold. Migrating the page may include sending an interrupt to a device driver. Migrating the page may include setting a write protection status for the page.

    SYSTEMS, METHODS, AND APPARATUS FOR COORDINATING COMPUTATION SYSTEMS
    28.
    发明申请
    SYSTEMS, METHODS, AND APPARATUS FOR COORDINATING COMPUTATION SYSTEMS 有权

    公开(公告)号：US20220374260A1

    公开(公告)日：2022-11-24

    申请号：US17686404

    申请日：2022-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tong ZHANG ,  Jing YANG ,  Rekha PITCHUMANI

    IPC: G06F9/48 ,  G06F9/54 ,  G06F9/455

    Abstract: A method for computation may include performing a first computation using a first system, wherein the first computation may be based, at least in part, on a first computation basis, performing a second computation using a second system, wherein the second computation may be based, at least in part, on a second computation basis, and coordinating the first computation and the second computation. The first computation basis may include a clock basis, and the second computation basis may include an event basis. The first computation may include a first operation, the second computation may include a second operation, and the coordinating the first computation and the second computation may include coordinating the first computation and the second computation based on the first operation and the second operation. The first operation may include an application computation operation, and the second operation may include a device computation operation.

    ERROR CORRECTION ON LENGTH-COMPATIBLE POLAR CODES FOR MEMORY SYSTEMS
    30.
    发明申请
    ERROR CORRECTION ON LENGTH-COMPATIBLE POLAR CODES FOR MEMORY SYSTEMS 有权

    公开(公告)号：US20220206895A1

    公开(公告)日：2022-06-30

    申请号：US17203745

    申请日：2021-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wei WU ,  Rekha PITCHUMANI ,  Zongwang LI

    IPC: G06F11/10 ,  H03M13/13 ,  G06F17/16

    Abstract: Inventive aspects include a polar code encoding system, which includes a partitioning unit to receive and partition input data into partitioned input data units. Encoders encode the partitioned input data units, and generate encoded partitioned input data units. Multiplier units perform matrix multiplication on the partitioned input data units and generator matrices, and generate matrix products. Adder units perform matrix addition on the encoded partitioned input data units and the matrix products. A combining unit combines outputs of the encoders into a target code word X. The target code word X may be a length-N code word X, where N=N1+N2+ . . . +Nm, where each of N1, N2, through Nm are a power of two (2).

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