FPGA ACCELERATION SYSTEM FOR MSR CODES
    21.
    发明公开

    公开(公告)号:US20230367675A1

    公开(公告)日:2023-11-16

    申请号:US18223019

    申请日:2023-07-17

    CPC classification number: G06F11/1076 G06F13/28

    Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

    SYSTEM AND METHOD FOR IN-SSD DATA PROCESSING ENGINE SELECTION BASED ON STREAM IDS

    公开(公告)号:US20230079467A1

    公开(公告)日:2023-03-16

    申请号:US18055371

    申请日:2022-11-14

    Abstract: A multi-stream memory system includes an in-device data processor including a first data processing engine and a second data processing engine, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform: identifying a stream ID of an input stream, identifying the first data processing engine as being associated with the stream ID based on a stream assignment table, and applying the first data processing engine to the input stream to generate processed data.

    SYSTEMS, METHODS, AND DEVICES FOR BIAS MODE MANAGEMENT IN MEMORY SYSTEMS

    公开(公告)号:US20220405207A1

    公开(公告)日:2022-12-22

    申请号:US17500927

    申请日:2021-10-13

    Abstract: A method for managing a memory system may include monitoring one or more accesses of a page of memory, determining, based on the monitoring, an access pattern of the page of memory, and selecting, based on the access pattern, a coherency bias for the page of memory. The monitoring may include maintaining an indication of the one or more accesses. The determining may include comparing the indication to a threshold. Maintaining the indication may include changing the indication in a first manner based on an access of the page of memory by a first apparatus. Maintaining the indication may include changing the indication in a second manner based on an access of the page of memory by a second apparatus. The first manner may counteract the second manner.

    SYSTEMS, METHODS, AND APPARATUS FOR PAGE MIGRATION IN MEMORY SYSTEMS

    公开(公告)号:US20220382478A1

    公开(公告)日:2022-12-01

    申请号:US17393399

    申请日:2021-08-03

    Abstract: A method for managing a memory system may include monitoring a page of a first memory of a first type, determine a usage of the page based on the monitoring, and migrating the page to a second memory of a second type based on the usage of the page. Monitoring the page may include monitoring a mapping of the page. Monitoring the mapping of the page may include monitoring a mapping of the page from a logical address to a physical address. Determining the usage of the page may include determining an update frequency of the page. Determining the usage of the page may include comparing the update frequency of the page to a threshold. Migrating the page may include sending an interrupt to a device driver. Migrating the page may include setting a write protection status for the page.

    SYSTEMS, METHODS, AND APPARATUS FOR COORDINATING COMPUTATION SYSTEMS

    公开(公告)号:US20220374260A1

    公开(公告)日:2022-11-24

    申请号:US17686404

    申请日:2022-03-03

    Abstract: A method for computation may include performing a first computation using a first system, wherein the first computation may be based, at least in part, on a first computation basis, performing a second computation using a second system, wherein the second computation may be based, at least in part, on a second computation basis, and coordinating the first computation and the second computation. The first computation basis may include a clock basis, and the second computation basis may include an event basis. The first computation may include a first operation, the second computation may include a second operation, and the coordinating the first computation and the second computation may include coordinating the first computation and the second computation based on the first operation and the second operation. The first operation may include an application computation operation, and the second operation may include a device computation operation.

    ERROR CORRECTION ON LENGTH-COMPATIBLE POLAR CODES FOR MEMORY SYSTEMS

    公开(公告)号:US20220206895A1

    公开(公告)日:2022-06-30

    申请号:US17203745

    申请日:2021-03-16

    Abstract: Inventive aspects include a polar code encoding system, which includes a partitioning unit to receive and partition input data into partitioned input data units. Encoders encode the partitioned input data units, and generate encoded partitioned input data units. Multiplier units perform matrix multiplication on the partitioned input data units and generator matrices, and generate matrix products. Adder units perform matrix addition on the encoded partitioned input data units and the matrix products. A combining unit combines outputs of the encoders into a target code word X. The target code word X may be a length-N code word X, where N=N1+N2+ . . . +Nm, where each of N1, N2, through Nm are a power of two (2).

    SYSTEMS AND METHODS FOR DISTRIBUTED IN-STORAGE COMPUTATION-CONSCIOUS ERASURE CODING

    公开(公告)号:US20220011935A1

    公开(公告)日:2022-01-13

    申请号:US16927798

    申请日:2020-07-13

    Abstract: A method includes sending, from an application layer, a chunk size setting to an erasure coding layer. The method further includes receiving, at the application layer, user data. The method further includes aligning, at the application layer, the user data based on the chunk size setting. The method further includes sending the aligned user data to the erasure coding layer. The method further includes partitioning, at the erasure coding layer, the aligned user data into a first data chunk and a second data chunk. The method further includes generating, at the erasure coding layer, a parity chunk based on the first data chunk and the second data chunk. The method further includes sending, from the erasure coding layer, the first data chunk, the second data chunk, and the parity chunk to a storage system.

    SYSTEM, DEVICE AND METHOD FOR STORAGE DEVICE ASSISTED LOW-BANDWIDTH DATA REPAIR

    公开(公告)号:US20190377637A1

    公开(公告)日:2019-12-12

    申请号:US16103907

    申请日:2018-08-14

    Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.

Patent Agency Ranking