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    Flip-flop
    21.
    发明授权
    Flip-flop 有权

    公开(公告)号：US10396761B2

    公开(公告)日：2019-08-27

    申请号：US15669072

    申请日：2017-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Chul Hwang ,  Min-Su Kim ,  Dae-Seong Lee

    IPC: H03K3/012 ,  H03K3/356 ,  H03K3/3562

    Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

    Semiconductor device and method for operating the same
    23.
    发明授权
    Semiconductor device and method for operating the same 有权
    半导体装置及其操作方法

    公开(公告)号：US09130550B2

    公开(公告)日：2015-09-08

    申请号：US14295802

    申请日：2014-06-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chung-Hee Kim ,  Min-Su Kim ,  Ji-Kyum Kim ,  Emil Kagramanyan ,  Dae-Seong Lee ,  Gun-Ok Jung ,  Uk-Rae Cho

    IPC: H03K3/289 ,  H03K3/037

    CPC classification number: H03K3/0372 ,  H03K3/0375

    Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.

    Abstract translation: 提供半导体器件和用于操作半导体器件的方法。 所述半导体器件包括：时钟生成单元，接收参考时钟;产生与所述参考时钟不同的第一和第二时钟; 第一锁存器，被配置为基于所述第一时钟接收输入数据并将所述输入数据输出为第一输出数据; 以及第二锁存器，被配置为基于所述第二时钟接收所述第一输出数据并将所述第一输出数据输出为第二输出数据，其中所述第一时钟的第一边缘不与所述第二时钟的第一边缘重叠，并且至少 第一时钟的第二边缘的一部分与第二时钟的第二边缘重叠。

    METHOD OF PREVENTING PROGRAM-DISTURBANCES FOR A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    24.
    发明申请
    METHOD OF PREVENTING PROGRAM-DISTURBANCES FOR A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    防止非易失性半导体存储器件的程序障碍的方法

    公开(公告)号：US20140043896A1

    公开(公告)日：2014-02-13

    申请号：US13939611

    申请日：2013-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Weon-Ho Park ,  Hyok-Ki Kwon ,  Min-Sup Kim ,  Min-Su Kim ,  Byoung-Ho Kim ,  Eui-Yeol Kim ,  Sang-Hoon Park ,  Ji-Hoon Park ,  Min-Jee Sung ,  Hyo-Soung Sim ,  Chang-Min Jeon ,  Hee-Seog Jeon

    IPC: G11C16/34

    CPC classification number: G11C16/3431 ,  G11C16/3427

    Abstract: A method of preventing program-disturbances for a non-volatile semiconductor memory device having a plurality of memory cells of which each includes a selection transistor and a memory transistor coupled in series between a bit-line and a common source-line is provided. First non-selected memory cells that share a first selection-line with a selected memory cell, and second non-selected memory cells that do not share the first selection-line with the selected memory cell are determined when the selected memory cell is selected to be programmed among the memory cells. A negative voltage is applied to second selection-lines that are coupled to the second non-selected memory cells when the selected memory cell is programmed by applying a positive voltage to the first selection-line that is coupled to the selected memory cell.

    Abstract translation: 提供一种防止具有多个存储单元的非易失性半导体存储器件的程序干扰的方法，每个存储单元中的每一个包括选择晶体管和串联耦合在位线和公共源极线之间的存储晶体管。 当选择的存储器单元被选择为为了选择存储单元时，与所选存储单元共享第一选择行的第一非选择存储单元和不与所选存储单元共享第一选择行的第二未选择存储单元 在存储单元之间进行编程。 当所选择的存储单元通过向耦合到所选存储单元的第一选择线施加正电压来编程时，将负电压施加到耦合到第二未选择存储单元的第二选择线。

    Flip-flop
    25.
    发明授权
    Flip-flop 有权

    公开(公告)号：US10911032B2

    公开(公告)日：2021-02-02

    申请号：US16524609

    申请日：2019-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Chul Hwang ,  Min-Su Kim ,  Dae-Seong Lee

    IPC: H03K3/012 ,  H03K3/3562 ,  H03K3/356

    Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

    Method of refreshing memory device and memory system based on storage capacity
    26.
    发明授权
    Method of refreshing memory device and memory system based on storage capacity 有权

    公开(公告)号：US10325643B2

    公开(公告)日：2019-06-18

    申请号：US15691828

    申请日：2017-08-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chang-Ho Yun ,  Min-Su Kim ,  Sung-Joon Kim ,  So-Ra Park ,  Hyun-Jung Yoo

    IPC: G06F3/06 ,  G11C11/406

    Abstract: A method of operating a memory device, a first setting signal is received by a first memory device among a plurality of memory devices. The first memory device has a first storage capacity, and the memory devices may be connected to one another by a single channel. A second setting signal is received by a second memory device among the plurality of memory devices. The second memory device has a second storage capacity different from the first storage capacity. N refresh operations are performed by the first memory device based on a first refresh command and the first setting signal during a first refresh period. M refresh operations are performed by the second memory device based on a second refresh command and the second setting signal during a second refresh period. A duration of the second refresh period is substantially the same as a duration of the first refresh period.

    Integrated circuit including complex logic cell
    27.
    发明授权
    Integrated circuit including complex logic cell 有权

    公开(公告)号：US10177166B2

    公开(公告)日：2019-01-08

    申请号：US15409674

    申请日：2017-01-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ju-Hyun Kang ,  Hyun Lee ,  Min-Su Kim ,  Ji-Kyum Kim ,  Jong-Woo Kim

    IPC: H01L27/118 ,  G06F17/50

    Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.

    Semiconductor circuits
    28.
    发明授权
    Semiconductor circuits 有权

    公开(公告)号：US10033386B2

    公开(公告)日：2018-07-24

    申请号：US15661153

    申请日：2017-07-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Chul Hwang ,  Min-Su Kim

    IPC: H03K19/018 ,  H03K3/037 ,  H03K19/0185 ,  H03K19/20 ,  H03K3/012 ,  H03K3/356

    Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

    Semiconductor Circuit
    30.
    发明申请
    Semiconductor Circuit 有权
    半导体电路

    公开(公告)号：US20150263730A1

    公开(公告)日：2015-09-17

    申请号：US14208053

    申请日：2014-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Min-Su Kim ,  Jin-Seung Son ,  Prashant Kenkare

    IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/00

    CPC classification number: H03K19/0185 ,  H03K19/0013 ,  H03K19/00361

    Abstract: A semiconductor circuit includes: a first circuit configured to provide first voltage to an output node when a voltage level of an input node is at a first level; a second circuit configured to provide second voltage to the output node when the voltage level of the input node is at a second level; and a third circuit configured to provide third voltage to the output node when the second voltage is provided to the output node, where the second circuit is turned off when the third voltage is provided to the output node.

    Abstract translation: 半导体电路包括：第一电路，被配置为当输入节点的电压电平处于第一电平时向输出节点提供第一电压; 第二电路，被配置为当输入节点的电压电平处于第二电平时，向输出节点提供第二电压; 以及第三电路，被配置为当所述第二电压被提供给所述输出节点时向所述输出节点提供第三电压，其中当所述第三电压被提供给所述输出节点时所述第二电路被关断。

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