知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

26 records (took 0.023 seconds)

    Semiconductor memory device and memory system including the same
    21.
    发明授权
    Semiconductor memory device and memory system including the same 有权

    公开(公告)号：US12175099B2

    公开(公告)日：2024-12-24

    申请号：US18302276

    申请日：2023-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungho Lee ,  Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Hyongryol Hwang

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    22.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US12148494B2

    公开(公告)日：2024-11-19

    申请号：US18115132

    申请日：2023-02-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyung-Soo Ha

    IPC: G11C29/42 ,  G11C11/406 ,  G11C29/20 ,  G11C29/44

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    23.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US12136463B2

    公开(公告)日：2024-11-05

    申请号：US18113702

    申请日：2023-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyungsoo Ha

    IPC: G11C29/00 ,  G11C29/20 ,  G11C29/42 ,  G11C29/44 ,  G11C29/12

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    25.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11615861B2

    公开(公告)日：2023-03-28

    申请号：US17374822

    申请日：2021-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyungsoo Ha

    IPC: G11C29/00 ,  G11C29/42 ,  G11C29/20 ,  G11C29/44 ,  G11C29/12

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

Patent Agency Ranking