公开(公告)号：US20250070790A1

公开(公告)日：2025-02-27

申请号：US18808348

申请日：2024-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minseob Lee ,  Sangmin Yoo ,  Joonhee Lee ,  Ikkyun Jo ,  Honggul Han

IPC: H03L7/197 ,  H03L7/097 ,  H03L7/099

Abstract: A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock signal of the PLL circuit, a phase detector configured to generate a phase error signal representing a phase difference between a first clock signal based on a reference clock signal and a second clock signal based on the output clock signal, a comparator configured to generate a phase error sign signal based on a reference voltage and the phase error signal, and a reference voltage generation circuit configured to scale first and second sign values of the phase error sign signal based on a fixed gain value and a variable gain value, respectively, and generate the reference voltage based on the scaled first and second sign values.

公开(公告)号：US20240040793A1

公开(公告)日：2024-02-01

申请号：US18486148

申请日：2023-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEJIE TAKAKI ,  Joonhee Lee

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L21/76895 ,  H01L21/76805 ,  H01L21/76843 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device includes a peripheral circuit region with a first substrate, circuit devices on the first substrate, and a first wiring structure, a memory cell region with a second substrate that has a first region and a second region, gate electrodes stacked in the first region, channel structures that penetrate the gate electrodes, a first horizontal conductive layer on the second substrate in the first region, an insulating region on the second substrate in the second region, a second horizontal conductive layer on the first horizontal conductive layer and the insulating region, and a second wiring structure, and a third wiring structure that connects the first substrate to the second substrate, and includes an upper via that penetrates the second horizontal conductive layer, the insulating region, and the second substrate, and a lower wiring structure connected to the upper.

公开(公告)号：US10741574B2

公开(公告)日：2020-08-11

申请号：US15955256

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseog Eun ,  Joonhee Lee

IPC: H01L27/11568 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11575

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.