公开(公告)号：US11545417B2

公开(公告)日：2023-01-03

申请号：US17162418

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea Jo ,  Ohguk Kwon ,  Namhoon Kim ,  Hyoeun Kim ,  Seunghoon Yeon

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00

Abstract: An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

公开(公告)号：US11152416B2

公开(公告)日：2021-10-19

申请号：US16507623

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Chajea Jo ,  Hyoeun Kim ,  Jongbo Shim ,  Sang-Uk Han

IPC: H01L31/00 ,  H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US20210013181A1

公开(公告)日：2021-01-14

申请号：US16742341

申请日：2020-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Han ,  Chajea Jo ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.

公开(公告)号：US20250149479A1

公开(公告)日：2025-05-08

申请号：US18660617

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haksun LEE ,  Dohyun Kim ,  Yeongseon Kim ,  Juhyeon Kim ,  Hyoeun Kim ,  Sunkyoung Seo ,  Chajea Jo

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/10

Abstract: A semiconductor chip includes: a substrate; a plurality of upper pads on the substrate, the plurality of upper pads including a first group of the upper pads and a second group of the upper pads; a buffer layer covering a side surface of the first group of the upper pads; and an insulating layer surrounding a side surface of the second group of the upper pads and a side surface of the buffer layer on the substrate, wherein the buffer layer includes a first material having a first Young's modulus smaller than a second Young's modulus of a second material in the plurality of upper pads.

公开(公告)号：US12021073B2

公开(公告)日：2024-06-25

申请号：US17656011

申请日：2022-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon Kim ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/03 ,  H01L24/80 ,  H01L24/94 ,  H01L24/97 ,  H01L24/08 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08146 ,  H01L2224/80001 ,  H01L2225/06541

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.

公开(公告)号：US11942446B2

公开(公告)日：2024-03-26

申请号：US17165429

申请日：2021-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Sunkyoung Seo ,  Seunghoon Yeon ,  Chajea Jo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L23/3157 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0657 ,  H01L2224/14181

Abstract: A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern.

公开(公告)号：US11735566B2

公开(公告)日：2023-08-22

申请号：US17375511

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ohguk Kwon ,  Namhoon Kim ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/065 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and at least one connection terminal between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and at least one upper pad on a top surface of the first semiconductor chip body and in contact with the at least one connection terminal, the at least one upper pad includes a recess that is downwardly recessed from a top surface thereof, and a depth of the recess is less than a thickness of the at least one upper pad.

公开(公告)号：US11710757B2

公开(公告)日：2023-07-25

申请号：US17227650

申请日：2021-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ohguk Kwon ,  Hyoeun Kim ,  Sunkyoung Seo ,  Sang-Uk Han

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/14634 ,  H01L23/481 ,  H01L24/08 ,  H01L24/73 ,  H01L24/89 ,  H01L27/1469 ,  H01L27/14627 ,  H01L2224/08146 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a molding layer, a silicon layer on the molding layer, a glass upwardly spaced apart from the silicon layer, and a connection dam coupled to the silicon layer and connecting the silicon layer to the glass. The silicon layer includes a silicon layer body, a silicon layer via extending vertically in the silicon layer body, and a micro-lens array on a top surface of the silicon layer body. A bottom surface of the silicon layer body contacts a top surface of the molding layer. The molding layer includes a molding layer body, a molding layer via that extends vertically in the molding layer body and has electrical connection with the silicon layer via, and a connection ball connected to a bottom surface of the molding layer via.

公开(公告)号：US20230119548A1

公开(公告)日：2023-04-20

申请号：US17873990

申请日：2022-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoeun Kim ,  Juhyeon Kim ,  Wonil Lee ,  Youngkun Jee

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.

公开(公告)号：US20220216186A1

公开(公告)日：2022-07-07

申请号：US17705872

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Han ,  Chajea Jo ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.