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    Electronic device and method for performing authentication
    21.
    发明授权
    Electronic device and method for performing authentication 有权

    公开(公告)号：US11157603B2

    公开(公告)日：2021-10-26

    申请号：US16344963

    申请日：2017-10-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Young Huh ,  Dae-Hyun Kim

    IPC: H04L9/00 ,  G06F21/32 ,  G06F21/34 ,  G06F21/45 ,  H04W12/06

    Abstract: The present invention relates to an electronic device and a method for performing authentication. The electronic device of the present invention comprises: a communication module; a memory; a processor electrically connected to the communication module and the memory; and an authentication module configured so as to be stored in the memory and executed by the processor, wherein the authentication module can be configured so as to transmit, on the basis of at least a part of a request, authentication information stored in the memory to an external electronic device, when the authentication request related to the external electronic device is obtained.

    Semiconductor memory devices and memory systems including the same
    22.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权

    公开(公告)号：US11036578B2

    公开(公告)日：2021-06-15

    申请号：US16217249

    申请日：2018-12-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dae-Hyun Kim ,  Yong-Gyu Chu ,  Jun Jin Kong ,  Ki-Jun Lee ,  Myung-Kyu Lee

    IPC: G06F11/10 ,  G11C29/52 ,  G06F13/16 ,  G11C11/401 ,  H01L25/065 ,  G11C11/4096 ,  G11C29/42 ,  G06F21/55

    Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

    Equalizer and semiconductor memory device including the same
    28.
    发明授权
    Equalizer and semiconductor memory device including the same 有权
    均衡器和包括其的半导体存储器件

    公开(公告)号：US09424897B2

    公开(公告)日：2016-08-23

    申请号：US14165990

    申请日：2014-01-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-Hyun Kim ,  Seung-Jun Bae ,  Kyung-Soo Ha

    IPC: G11C7/22 ,  H03K19/003 ,  G11C7/10 ,  H03K19/094

    CPC classification number: G11C7/22 ,  G11C7/1048 ,  G11C7/1057 ,  H03K19/00361 ,  H03K19/09429

    Abstract: Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.

    Abstract translation: 提供了一种均衡器和包括该均衡器的半导体存储器件。 均衡器包括延迟电路和反相电路。 延迟电路被配置为响应于选择信号输出延迟施加到输入/输出节点的输入信号的延迟信号和反相输入信号的反相信号之一。 反相电路被配置为反转从延迟电路提供的信号并将反相信号输出到输入/输出节点。 均衡器被配置为使得当延迟电路输出延迟信号时，均衡器作为放大输入信号并输出​​放大的输入信号的感应偏置电路工作，并且当延迟电路输出反相信号时，均衡器作为锁存器 电路存储和输出输入信号。

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