Display substrate comprising a plurality of conductive patterns

    公开(公告)号:US09666613B2

    公开(公告)日:2017-05-30

    申请号:US14247818

    申请日:2014-04-08

    CPC classification number: H01L27/1244 H01L27/124 H01L27/1248 H01L27/1259

    Abstract: A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.

    Thin film transistor array panel
    25.
    发明授权
    Thin film transistor array panel 有权
    薄膜晶体管阵列面板

    公开(公告)号:US09515096B2

    公开(公告)日:2016-12-06

    申请号:US14838055

    申请日:2015-08-27

    Abstract: The present disclosure provides a thin film transistor array. In an exemplary embodiment, the thin film transistor array includes: a substrate; a gate line including a gate pad and disposed on the substrate; a gate insulating layer disposed on the gate line and the gate pad; a data line including a data pad and disposed on the gate insulating layer; a first passivation layer disposed on the data line; a first electrode disposed on the first passivation layer; a second passivation layer disposed on the first electrode; and a second electrode disposed on the second passivation layer. The gate pad is exposed through a first contact hole, and the gate insulating layer, the first passivation layer, and the second passivation layer include at least a portion of the first contact hole.

    Abstract translation: 本发明提供一种薄膜晶体管阵列。 在示例性实施例中,薄膜晶体管阵列包括:衬底; 栅极线,包括栅极焊盘并设置在所述衬底上; 设置在栅极线和栅极焊盘上的栅极绝缘层; 数据线,包括数据焊盘并设置在栅极绝缘层上; 设置在所述数据线上的第一钝化层; 设置在所述第一钝化层上的第一电极; 设置在所述第一电极上的第二钝化层; 以及设置在所述第二钝化层上的第二电极。 栅极焊盘通过第一接触孔露出,栅极绝缘层,第一钝化层和第二钝化层包括第一接触孔的至少一部分。

    LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME
    26.
    发明申请
    LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME 审中-公开
    液晶显示器及其制造方法

    公开(公告)号:US20150346529A1

    公开(公告)日:2015-12-03

    申请号:US14674752

    申请日:2015-03-31

    CPC classification number: G02F1/136227 G02F1/133512 G02F1/136213

    Abstract: A liquid crystal display (LCD) and a method of manufacturing the same are disclosed. In one aspect, the LCD comprises a first substrate, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first and second substrates. The first substrate comprises a first insulating substrate, a thin film transistor (TFT) formed over the first insulating substrate and including a drain electrode, and an insulating layer covering the TFT and comprising upper and lower portions having different heights, wherein the insulating layer has an opening formed through the lower portion so as to expose the drain electrode. The first substrate also comprises a reference electrode formed over the insulating layer, an inter-insulating electrode covering the reference electrode, and a pixel electrode formed over the inter-insulating layer and electrically connected to the drain electrode through the opening.

    Abstract translation: 公开了一种液晶显示器(LCD)及其制造方法。 一方面,LCD包括第一衬底,面对第一衬底的第二衬底和插在第一和第二衬底之间的液晶层。 第一衬底包括第一绝缘衬底,形成在第一绝缘衬底上并包括漏电极的薄膜晶体管(TFT)和覆盖TFT的绝缘层,并且包括具有不同高度的上部和下部,其中绝缘层具有 通过下部形成的开口,露出漏电极。 第一基板还包括形成在绝缘层上的参考电极,覆盖参考电极的绝缘电极和形成在绝缘层之上并通过开口电连接到漏电极的像素电极。

    MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL
    27.
    发明申请
    MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL 审中-公开
    薄膜晶体管阵列的制造方法

    公开(公告)号:US20130306974A1

    公开(公告)日:2013-11-21

    申请号:US13952059

    申请日:2013-07-26

    CPC classification number: H01L29/786 H01L27/124 H01L27/1259 H01L29/78645

    Abstract: A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.

    Abstract translation: 薄膜晶体管阵列板的制造方法包括:使用非过氧化物的蚀刻剂,在基板上同时形成栅极导体和第一电极; 在所述栅极导体和所述第一电极上形成栅极绝缘层; 在栅极绝缘层上形成半导体,源电极和漏电极; 在半导体,源电极和漏电极上形成钝化层; 以及在所述钝化层上形成第二电极层。

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