Abstract:
A display panel includes a 1-1st sub-pixel and a 1-2nd sub-pixel disposed in a first row, a 2-1st sub-pixel disposed in a second row and a 3-1st sub-pixel and a 3-2nd sub-pixel disposed in a third row. A first data line extends from the first row to the third row and electrically connects a pixel circuit of the 1-1st sub-pixel, a pixel circuit of the 2-1st sub-pixel, and a pixel circuit of the 3-1st sub-pixel. A 2-1st data line is electrically connected to a pixel circuit of the 1-2nd sub-pixel. A 2-2nd data line is electrically connected to a pixel circuit of the 3-2nd sub-pixel. A first bridge line is disposed on a different layer than the data lines and contacts the 2-1st data line and the 2-2nd data line and includes an overlapping portion extending along at least a portion of the first data line.
Abstract:
A display panel includes sub-pixels each including a light-emitting element and a pixel circuit including a first transistor and a second transistor; a timing control unit to generate bias data based on first characteristic information of the first transistor, and generate correction data based on second characteristic information of the second transistor; and a data sensing driving unit configured to receive the bias data and the correction data, and output a bias voltage and a grayscale voltage to the pixel circuit. The pixel circuit includes the first transistor to output a driving current to the light-emitting element; a first driving circuit to control a magnitude of the driving current based on the bias voltage; and a second driving circuit including the second transistor and configured to control a pulse width of the driving current based on the grayscale voltage.
Abstract:
A display device including: a display panel including a gate line and a data line; and a shift register including a stage for driving the gate line. The stage may include a first driving unit in a display area of the display panel and a second driving unit in a non-display area of the display panel.
Abstract:
Provided is a method of manufacturing TFT substrate, the method including: forming a first conductive layer and a gate electrode; forming a gate insulating layer covering the first conductive layer and the gate electrode; forming a first contact hole exposing the first conductive layer through the gate insulating layer; forming, on the gate insulating layer of a pixel area, an oxide semiconductor pattern comprising a first region which is conductive, a second region which is conductive, and a third region between the first region and the second region; forming a source electrode contacting the first region of the oxide semiconductor pattern, a drain electrode contacting the second region of the oxide semiconductor pattern and a second conductive layer contacting the first conductive layer on a non-pixel area. Each of the first region and the second region overlaps the gate electrode.
Abstract:
A gate driving circuit includes a plurality of driving stages applying gate signals to gate lines of a display panel. Among the plurality of driving stages, a k-th (k being a natural number equal to or greater than 2) includes a first node, an output part that is connected to the first node and outputs a k-th gate signal in response to a voltage of the first node, a control part that controls an electric potential of the first node, an inverter part that outputs a k-th switching signal, and a pull-down part that receives a (k−1)th switching signal from a (k−1)th driving stage of the plurality of driving stages and lowers a voltage of the output part in response to the (k−1)th switching signal.
Abstract:
A display device includes: a display panel having a display area and a non-display area; a plurality of pixels on the display area to emit light, wherein pixels arranged along a first direction are defined as first pixel groups and pixels arranged along a second direction are defined as second pixel groups; gate driving units on the display area to generate gate signals, wherein the gate driving units include first and second gate driving units corresponding one-to-one with each other; a data driver on the non-display area to generate data signals; a plurality of first lines to transmit the data signals to the plurality of pixels; and a plurality of second lines to transmit driving start signals from the first gate driving units to the second gate driving units respectively corresponding to the first gate driving units, wherein the first or second lines are between the first groups.
Abstract:
A nanocrystal display device includes a plurality of pixels; a gate line extended in a row direction; a data line extended in a column direction; and a second insulating layer on the data line. Each pixel includes first and second pixel areas adjacent to each other in the column direction; first and second pixel electrodes on the second insulating layer of the first and second pixel areas; a first black matrix on the second insulating layer, and having a step difference greater than that of the first and second pixel electrodes; a common electrode extended in the row direction, contacting the first black matrix and spaced apart from the second insulating layer in the first and second pixel areas, and a tunnel-shaped cavity between the common electrode, the first black matrix and the second insulating layer; and a liquid crystal layer in the tunnel-shaped cavity.
Abstract:
A display device is disclosed. In one aspect, the display device includes a timing controller configured to receive an image signal and a control signal and output a mode signal and a gate pulse signal based on the image signal and the control signal, wherein the mode signal has a voltage level and wherein the gate pulse signal has a frequency. The display device further includes a clock generator configured to generate a gate clock signal based on the mode signal and the gate pulse signal, wherein the gate clock signal has a voltage level and wherein the clock generator is further configured to set the voltage level of the gate clock signal based at least in part on the mode signal. The display device includes gate lines and a gate driver configured to drive gate lines based at least in part on the gate clock signal.
Abstract:
A display panel, a pixel circuit, and a display device are disclosed. The display panel includes sub-pixels and a driver driving the sub-pixels. Each sub-pixel includes: an emission element; a first transistor configured to generate a driving current; a constant current control circuit configured to receive a reference voltage and a bias voltage for setting a value of the driving current and including a first capacitor configured to store a first compensation voltage generated by adding a threshold voltage of the first transistor to a difference between the bias voltage and the reference voltage; and a pulse width control circuit configured to receive a data voltage used to determine an emission duration of the emission element and including a second transistor configured to control a pulse width of the driving current according to the data voltage and a second capacitor configured to store a second compensation voltage corresponding to a threshold voltage of the second transistor.
Abstract:
A gate driving circuit includes a plurality of driving stages, wherein an ith (where i is a natural number of 2 or more) driving stage among the plurality of driving stages includes: a output unit outputting an ith output signal including a high voltage generated based on a clock signal in response to a low voltage at a Q-node; a stabilization unit providing the low voltage to the Q-node in response to a switching signal applied to an A-node after the ith output signal is outputted; and an inverter unit outputting the switching signal for controlling the stabilization unit to the A-node.