公开(公告)号：USD886845S1

公开(公告)日：2020-06-09

申请号：US29685299

申请日：2019-03-27

Applicant: Samsung Electronics Co., Ltd.

Designer： Daewon Kim ,  Hyun Yeul Lee ,  Insheik Martin Jung ,  Hyosang Bang ,  Youngseong Kim ,  Jaewon Park ,  Jiyoung Han

公开(公告)号：US11810964B2

公开(公告)日：2023-11-07

申请号：US17060193

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongseok Suh ,  Daewon Kim ,  Beomjin Park ,  Sukhyung Park ,  Sungil Park ,  Jaehoon Shin ,  Bongseob Yang ,  Junggun You ,  Jaeyun Lee

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L29/772 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/78696 ,  H01L21/28141 ,  H01L21/823468 ,  H01L29/1037 ,  H01L29/66719 ,  H01L29/7727

Abstract: A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

公开(公告)号：US20220165729A1

公开(公告)日：2022-05-26

申请号：US17382956

申请日：2021-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehoon Shin ,  Bongseok Suh ,  Daewon Kim ,  Sukhyung Park ,  Junggun You ,  Jaeyun Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

公开(公告)号：US11171133B2

公开(公告)日：2021-11-09

申请号：US16927636

申请日：2020-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin Park ,  Dongil Bae ,  Daewon Kim ,  Taeyoung Kim ,  Joohee Jung ,  Jaehoon Shin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423

Abstract: A semiconductor device includes an active pattern extending on a substrate in a first direction, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; first, second and third channel layers vertically separated and sequentially disposed on the active pattern; a first gate electrode extending in a second direction, intersecting the active pattern, and surrounding the first, second and third channel layers; source/drain regions disposed on the active pattern, on at least one side of the first gate electrode, and contacting the first, second and third channel layers; a semiconductor structure including first semiconductor layers and second semiconductor layers alternately stacked on the active pattern, and having a second edge portion exposed toward the separation region; and a blocking layer covering at least one of an upper surface, side surfaces, or the second edge portion, of the semiconductor structure.

公开(公告)号：USD926219S1

公开(公告)日：2021-07-27

申请号：US29701870

申请日：2019-08-15

Applicant: Samsung Electronics Co., Ltd.

Designer： Jiwon Yoo ,  Hyemi Yu ,  Daewon Kim

公开(公告)号：USD909405S1

公开(公告)日：2021-02-02

申请号：US29653189

申请日：2018-06-13

Applicant: Samsung Electronics Co., Ltd.

Designer： Daewon Kim ,  Hyun Yeul Lee ,  Insheik Martin Jung ,  Hyosang Bang ,  Youngseong Kim ,  Jaewon Park ,  Jiyoung Han

公开(公告)号：US10903216B2

公开(公告)日：2021-01-26

申请号：US16520730

申请日：2019-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Daewon Kim ,  Dongjin Lee

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4097

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.

公开(公告)号：USD872116S1

公开(公告)日：2020-01-07

申请号：US29657869

申请日：2018-07-26

Applicant: Samsung Electronics Co., Ltd.

Designer： Daewon Kim ,  Jaewon Park ,  Hyunyeul Lee ,  Jiyoung Han ,  Hyungmin Kim

公开(公告)号：US20250133819A1

公开(公告)日：2025-04-24

申请号：US19001750

申请日：2024-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehoon Shin ,  Bongseok Suh ,  Daewon Kim ,  Sukhyung Park ,  Junggun You ,  Jaeyun Lee

IPC: H10D84/85 ,  H01L21/02 ,  H01L21/28 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D64/23 ,  H10D64/27 ,  H10D64/66 ,  H10D84/01 ,  H10D84/03

Abstract: A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

公开(公告)号：US20240038873A1

公开(公告)日：2024-02-01

申请号：US18483413

申请日：2023-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongseok Suh ,  Daewon Kim ,  Beomjin Park ,  Sukhyung Park ,  Sungil Park ,  Jaehoon Shin ,  Bongseob Yang ,  Junggun You ,  Jaeyun Lee

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/78696 ,  H01L29/66553 ,  H01L29/7727

Abstract: A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.