公开(公告)号：US10685837B2

公开(公告)日：2020-06-16

申请号：US16240216

申请日：2019-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ik Oh ,  Daehyun Jang ,  Ha-Na Kim ,  Kyoungsub Shin

IPC: H01L21/027 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/306 ,  H01L21/308 ,  H01L27/11556 ,  H01L27/24 ,  H01L25/065 ,  H01L25/00 ,  H01L27/11521 ,  H01L45/00

Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.

公开(公告)号：US10522350B2

公开(公告)日：2019-12-31

申请号：US15808993

申请日：2017-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hyun Kwon ,  Daehyun Jang

IPC: H01L21/033 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11565

Abstract: A method of fabricating a three-dimensional semiconductor device comprises stacking first hardmask layers and second hardmask layers on a lower layer including a pattern region and a buffer region adjacent to the pattern region, the second hardmask layers and the first hardmask layers for forming a first hardmask pattern and a second hardmask pattern, patterning the second hardmask layer to form the second hardmask pattern including a plurality of first mask holes on the pattern region and at least one recess on the buffer region, the plurality of first mask holes exposing the first hardmask layer, and etching the first hardmask layer using the second hardmask pattern as an etch mask to form the first hardmask pattern including a plurality of etch mask holes on the pattern region and at least one buffer mask hole on the buffer region, the plurality of etch mask holes exposing a top surface of the lower layer, the at least one buffer mask hole having a bottom surface spaced apart from the top surface of the lower layer.

公开(公告)号：US20190066983A1

公开(公告)日：2019-02-28

申请号：US15945001

申请日：2018-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Edward Sung ,  Hyuk Kim ,  Daehyun Jang ,  Sung II Cho

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/683

Abstract: Shrouds and substrate treating systems including the same are provided. Substrate treating systems may include a process chamber, a supporter, and a plasma source that is spaced apart from the supporter in a vertical direction. The substrate treating systems may also include a shroud configured to contain the plasma therein. The shroud may include a sidewall portion and a first flange portion extending horizontally from the sidewall portion and including a plurality of first slits that extend through a thickness of the first flange portion. The first flange portion may define a first opening, and a portion of the supporter may extend through the first opening. The sidewall portion may include a plurality of second slits, and each of the plurality of second slits may extend through a thickness of the sidewall portion and may extend from one of the plurality of first slits toward the plasma source.