公开(公告)号：US20220173056A1

公开(公告)日：2022-06-02

申请号：US17108298

申请日：2020-12-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA

IPC: H01L23/64 ,  H01F27/00

Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.

公开(公告)号：US20210249314A1

公开(公告)日：2021-08-12

申请号：US17121175

申请日：2020-12-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta MIZUKAMI ,  Tohru KAWAI

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/225 ,  H01L29/49

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer, a semiconductor layers and a silicide layer. The insulating layer is formed on the semiconductor substrate. The semiconductor layer is formed on the insulating layer and includes a polycrystalline silicon. The silicide layer is formed on the semiconductor layer. The semiconductor layer has a first semiconductor part and a second semiconductor part. The first semiconductor part includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type. The second semiconductor part is adjacent the second semiconductor region. In a width direction of the first semiconductor part, a second length of the second semiconductor part is greater than a first length of the first semiconductor part. A distance between the first and second semiconductor regions is 100 nm or more in an extension direction in which the first semiconductor region extends.

公开(公告)号：US20190196231A1

公开(公告)日：2019-06-27

申请号：US16182259

申请日：2018-11-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tohru KAWAI ,  Shinichi WATANUKI ,  Yasutaka NAKASHIBA

IPC: G02F1/025

CPC classification number: G02F1/025 ,  G02F2201/063 ,  G02F2203/50

Abstract: The performances of a semiconductor device are improved. The semiconductor device includes an insulation layer, an optical waveguide part formed over the insulation layer, and including a p type semiconductor region and an n type semiconductor region formed therein, and an interlayer insulation film formed over the insulation layer in such a manner as to cover the optical waveguide part. At the first portion of the optical waveguide part, in a cross sectional view perpendicular to the direction of extension of the optical waveguide part, the n type semiconductor region is arranged at the central part of the optical waveguide part, and the p type semiconductor region is arranged in such a manner as to surround the entire circumference of the n type semiconductor region.

公开(公告)号：US20190165165A1

公开(公告)日：2019-05-30

申请号：US16263256

申请日：2019-01-31

Applicant: Renesas Electronics Corporation

Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA ,  Yutaka AKIYAMA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L23/482 ,  H01L27/06 ,  H01L29/739 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L23/495 ,  H01L23/522

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

公开(公告)号：US20170153390A1

公开(公告)日：2017-06-01

申请号：US15363663

申请日：2016-11-29

Applicant: Renesas Electronics Corporation

Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA

IPC: G02B6/122 ,  H01L23/522 ,  H01L21/265 ,  H01L21/768 ,  H01L29/36 ,  H01L23/528

CPC classification number: G02B6/122 ,  G02B6/12004 ,  G02B2006/12061 ,  G02B2006/12123 ,  G02B2006/12142 ,  G02B2006/12176 ,  H01L21/26506 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/36

Abstract: Provided is an SOI substrate which has a substrate, an insulating layer formed over the substrate, and a semiconductor layer formed over the insulating layer. Optical waveguides are formed in the semiconductor layer of the SOI substrate. This substrate has a low resistance semiconductor layer and a high resistance semiconductor layer thereover. Further, wirings which are formed through insulating films are provided on the optical waveguides. In this manner, the low resistance semiconductor layer is arranged in the surface part of the substrate of the insulating films, thereby restraining an eddy current generated in the substrate due to an electric signal transmitted through the wirings.