公开(公告)号：US09064077B2

公开(公告)日：2015-06-23

申请号：US13792384

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Yang Du

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/66

Abstract: The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology.

Abstract translation: 所公开的实施例涉及用于使用提供对现有3D设计方法的显着改进的2D和3D块的混合来布局规划集成电路设计的系统和方法。 所公开的实施例提供了更好的平面图解决方案，其进一步最小化电线长度并提高设计的整体功率/性能包络。 所公开的方法可以用于构建新的3D IP块，以用于使用单片3D集成技术构建的设计中。

公开(公告)号：US20150132922A1

公开(公告)日：2015-05-14

申请号：US14598293

申请日：2015-01-16

Applicant: QUALCOMM Incorporated

Inventor： Yang Du

IPC: H01L21/762 ,  H01L21/82 ,  H01L21/306

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/30625 ,  H01L21/82 ,  H01L21/8221 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ion-reduced, ion cut-formed three-dimensional (3D) integrated circuits (IC) (3DICs) are disclosed. Related methods and systems are also disclosed. During an ion-cut process for forming a monolithic 3DIC, extra ions are implanted in the donor wafer to effectuate the ion-cut. Excess, residual implanted ions remain implanted in a top layer of the transfer layer of the 3DIC. However, these residual implanted ions can interfere with operation of electronic components in the 3DIC. In this regard, the 3DIC and methods disclosed herein involve reduction or removal of the residual extra ions before further electronic components are created and layered in a 3DIC. In this manner, the extra charge elements introduced by such extra ions are reduced or removed providing for better functionality in the completed device.

Abstract translation: 公开了离子还原的离子切割形成的三维（3D）集成电路（IC）（3DIC）。 还公开了相关方法和系统。 在用于形成单片3DIC的离子切割工艺期间，在施主晶片中注入额外的离子以实现离子切割。 剩余的注入离子保留注入到3DIC的转移层的顶层中。 然而，这些残留的注入离子可能会干扰3DIC中电子元件的操作。 在这方面，本文公开的3DIC和方法涉及在创建其它电子部件之前还原或去除剩余的额外离子，并且在3DIC中分层。 以这种方式，通过这种额外的离子引入的额外的电荷元素被减少或去除，从而在完成的器件中提供更好的功能。

公开(公告)号：US20150112646A1

公开(公告)日：2015-04-23

申请号：US14132377

申请日：2013-12-18

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du ,  Kambiz Samadi

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/06

Abstract: Methods of designing three dimensional integrated circuits (3DIC) and related systems and components are disclosed. An exemplary embodiment provides an improved cell library for use with existing place and route software in such a manner that the modified software allows building 3DICs. The improved cell library includes 3D cells that have the footprint of the cell projected onto a two dimensional (2D) image. The projected view may then be discounted to the portion of the cell that is within an upper tier so that the cell appears to the place and route software to be a 2D cell. The discounted 2D image is then used by the place and route software. Such cells allow a circuit designer to leverage the existing 2D place and route tools as well as static timing analysis tools.

Abstract translation: 公开了设计三维集成电路（3DIC）及相关系统和组件的方法。 示例性实施例提供了一种改进的小区库，其用于与现有的位置和路由软件一起使用，使得修改的软件允许构建3DIC。 改进的细胞库包括具有投影到二维（2D）图像上的细胞的足迹的3D细胞。 然后可以将投影视图折扣到上层内的单元的部分，使得单元格出现在该位置并将软件路由为2D单元。 打折的2D图像然后由地方和路线软件使用。 这样的单元允许电路设计者利用现有的2D位置和路径工具以及静态时序分析工具。

公开(公告)号：US20150109843A1

公开(公告)日：2015-04-23

申请号：US14152248

申请日：2014-01-10

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du ,  Kambiz Samadi

IPC: G11C5/02 ,  H01L23/00 ,  H04L12/933

CPC classification number: G11C5/02 ,  G06F1/3225 ,  G06F1/3275 ,  G11C5/025 ,  G11C5/063 ,  H01L24/89 ,  H01L27/0688 ,  H01L2924/1434 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/13 ,  Y02D10/14

Abstract: Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components are disclosed. A 3D memory crossbar architecture with tight-pitched vertical monolithic intertier vias (MIVs) for inter-block routing and multiplexers at each tier for block access is used to shorten overall conductor length and reduce resistive-capacitive (RC) delay. Elimination of such long crossbars reduces the RC delay of the crossbar and generally improves performance and speed. Further, elimination of the long horizontal crossbars makes conductor routing easier. The MIVs, with their small run-length, can work without the need for repeaters (unlike the long crossbars), and control logic may be used to configure the memory banks based on use.

Abstract translation: 公开了具有垂直存储器组件的单片三维（3D）集成电路（IC）（3DIC）。 使用具有用于块间路由选择的紧密垂直单片中间层通道（MIV）的三维存储器交叉结构架构，用于块访问的每层级多路复用器，以缩短整体导体长度并降低电阻 - 电容（RC）延迟。 消除这种长的十字准线会降低交叉开关的RC延迟，并通常提高性能和速度。 此外，消除长的横向横梁使得导线布线更容易。 MIVs具有较小的长度，可以在不需要中继器的情况下工作（与长十字准线不同），并且可以使用控制逻辑来基于使用配置存储体。

公开(公告)号：US09013235B2

公开(公告)日：2015-04-21

申请号：US14012445

申请日：2013-08-28

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: H01L25/00 ,  H03K3/037 ,  G06F17/50

CPC classification number: H03K3/0372 ,  G06F17/5068 ,  H01L27/0688 ,  H03K3/35625

Abstract: Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier, thus potentially giving better setup, hold and clock-to-q margin. In particular, a first tier of the 3DIC has the master latch, slave latch, and clock circuit. A second tier has the input circuit and the output circuit.

Abstract translation: 公开了具有最小时钟偏移和相关系统和方法的单片三维（3D）触发器。 本公开提供了具有翻转的3D集成电路（3DIC）（3DIC），其跨越3DIC的至少两层。 触发器分为跨级别，晶体管分区，使得所有与时钟相关的器件保持在同一层级，从而可能提供更好的设置，保持和时钟到余裕。 特别地，3DIC的第一层具有主锁存器，从锁存器和时钟电路。 第二层有输入电路和输出电路。

公开(公告)号：US20150019802A1

公开(公告)日：2015-01-15

申请号：US14012478

申请日：2013-08-28

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C5/025 ,  G11C8/12 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/11

Abstract: A monolithic three dimensional (3D) memory cell array architecture with bitcell and logic partitioning is disclosed. A 3D integrated circuit (IC) (3DIC) is proposed which folds or otherwise stacks elements of the memory cells into different tiers within the 3DIC. Each tier of the 3DIC has memory cells as well as access logic including global block control logic therein. By positioning the access logic and global block control logic in each tier with the memory cells, the length of the bit and word lines for each memory call are shortened, allowing for reduced supply voltages as well as generally reducing the overall footprint of the memory device.

Abstract translation: 公开了一种具有位单元和逻辑分区的单片三维（3D）存储单元阵列架构。 提出了3D集成电路（IC）（3DIC），其将存储器单元的元素折叠或以其它方式叠加到3DIC内的不同层中。 3DIC的每一层具有存储单元以及包括其中的全局块控制逻辑的访问逻辑。 通过将访问逻辑和全局块控制逻辑定位在具有存储器单元的每个层中，每个存储器调用的位和字线的长度被缩短，允许减小的电源电压以及通常减小存储器件的总体占用 。

公开(公告)号：US20140149958A1

公开(公告)日：2014-05-29

申请号：US13792384

申请日：2013-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Yang Du

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/66

Abstract: The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology.

Abstract translation: 所公开的实施例涉及用于使用提供对现有3D设计方法的显着改进的2D和3D块的混合来布局规划集成电路设计的系统和方法。 所公开的实施例提供了更好的平面图解决方案，其进一步最小化电线长度并提高设计的整体功率/性能包络。 所公开的方法可以用于构建新的3D IP块，以用于使用单片3D集成技术构建的设计中。

公开(公告)号：US11609623B2

公开(公告)日：2023-03-21

申请号：US16119929

申请日：2018-08-31

Applicant: QUALCOMM Incorporated

Inventor： Yu Pu ,  Yang Du

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3296 ,  G06N3/063 ,  G06N3/04

Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.

公开(公告)号：US20190027435A1

公开(公告)日：2019-01-24

申请号：US16144127

申请日：2018-09-27

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/528 ,  H01L25/00 ,  H01L23/522 ,  H01L27/06 ,  H01L23/48 ,  H01L25/065

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：US20180259581A1

公开(公告)日：2018-09-13

申请号：US15455253

申请日：2017-03-10

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen ,  Wah Nam Hsu ,  Yang Du

IPC: G01R31/3185 ,  H01L21/66 ,  H01L27/06 ,  H01L23/528 ,  H01L23/34 ,  H03K3/03 ,  H03K17/14

CPC classification number: G01R31/318513 ,  G01R31/318505 ,  H01L22/34 ,  H01L23/34 ,  H01L23/5286 ,  H01L25/0657 ,  H01L27/0688 ,  H03K3/0315 ,  H03K17/14

Abstract: Dynamically controlling voltage provided to three-dimensional (3D) integrated circuits (ICs) (3DICs) to account for process variations measured across interconnected IC tiers of 3DICs are disclosed herein. In one aspect, a 3DIC process variation measurement circuit (PVMC) is provided to measure process variation. The 3DIC PVMC includes stacked logic PVMCs configured to measure process variations of devices across multiple IC tiers and process variations of vias that interconnect multiple IC tiers. The 3DIC PVMC may include IC tier logic PVMCs configured to measure process variations of devices on corresponding IC tiers. These measured process variations can be used to dynamically control supply voltage provided to the 3DIC such that operation of the 3DIC approaches a desired process corner. Adjusting supply voltage using the 3DIC PVMC takes into account interconnected properties of the 3DIC such that the supply voltage is adjusted to cause the 3DIC to operate in the desired process corner.