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    Charge pump power savings
    22.
    发明授权
    Charge pump power savings 有权
    充电泵省电

    公开(公告)号：US09312755B2

    公开(公告)日：2016-04-12

    申请号：US13785601

    申请日：2013-03-05

    Applicant: QUALCOMM Incorporated

    Inventor： Le Wang ,  Vijayakumar Dhanasekaran

    IPC: H03B1/00 ,  H03K3/00 ,  H02M3/07

    CPC classification number: H02M3/07 ,  H02M2003/071

    Abstract: Exemplary embodiments are directed to systems, devices, methods, and computer-readable media for reducing static and dynamic power consumption of a charge pump. In one embodiment, a device may include a plurality of switches, each switch of the plurality having a gate coupled to a dedicated driver of a plurality of drivers. The device may further include at least one clamp switch coupled to at least one driver of the plurality of drivers and configured to adjust a rail voltage of the at least one driver if an input voltage is greater than a threshold voltage. In another embodiment, the device may include a plurality of multiplexers, each multiplexer of the plurality of multiplexers coupled to a portion of an associated switch of the plurality of switches and configured to disable the portion of the associated switch if a clock frequency of the charge pump is below a threshold frequency.

    Abstract translation: 示例性实施例涉及用于减少电荷泵的静态和动态功耗的系统，设备，方法和计算机可读介质。 在一个实施例中，设备可以包括多个开关，多个开关中的每个开关具有耦合到多个驱动器的专用驱动器的栅极。 该装置还可以包括耦合到多个驱动器中的至少一个驱动器的至少一个钳位开关，并被配置为如果输入电压大于阈值电压则调整至少一个驱动器的轨道电压。 在另一个实施例中，设备可以包括多个多路复用器，多个复用器的每个多路复用器耦合到多个交换机中的相关联的开关的一部分，并且被配置为如果电荷的时钟频率 泵低于阈值频率。

    SLEW RATE CONTROL BOOST CIRCUITS AND METHODS
    23.
    发明申请
    SLEW RATE CONTROL BOOST CIRCUITS AND METHODS 有权
    高速率控制提升电路和方法

    公开(公告)号：US20150381120A1

    公开(公告)日：2015-12-31

    申请号：US14533928

    申请日：2014-11-05

    Applicant: QUALCOMM Incorporated

    Inventor： Xin Fan ,  Vijayakumar Dhanasekaran

    IPC: H03F1/32 ,  H03F3/04 ,  H03F1/02

    CPC classification number: H03F1/32 ,  H03F1/0205 ,  H03F1/0266 ,  H03F1/086 ,  H03F1/3217 ,  H03F3/04 ,  H03F3/185 ,  H03F3/3023 ,  H03F2200/03 ,  H03F2200/18 ,  H03F2200/555 ,  H03F2201/3215 ,  H03F2203/30105 ,  H03F2203/45248

    Abstract: The present disclosure amplifier circuits and methods having boosted slew rates. In one embodiment, an amplifier circuit comprises an output stage comprising a first output transistor, the first output transistor comprising a gate, a source, and a drain, wherein the gate receives a signal to be amplified. A bias circuit biases the gate of the first output transistor. A damping circuit is coupled the gate of the first output transistor and is configured to produce a high impedance at low frequencies and a low impedance at high frequencies. The damping circuit includes a current limit circuit to limit current to the gate of the first output transistor when a voltage on the gate of the first output transistor decreases in response to the signal.

    Abstract translation: 本公开的放大器电路和方法具有升压转换速率。 在一个实施例中，放大器电路包括输出级，其包括第一输出晶体管，第一输出晶体管包括栅极，源极和漏极，其中栅极接收待放大的信号。 偏置电路偏置第一输出晶体管的栅极。 阻尼电路耦合第一输出晶体管的栅极，并被配置为在低频下产生高阻抗，在高频下产生低阻抗。 当第一输出晶体管的栅极上的电压响应于该信号而减小时，阻尼电路包括电流限制电路，以限制到第一输出晶体管的栅极的电流。

    CHARGE PUMP POWER SAVINGS
    24.
    发明申请
    CHARGE PUMP POWER SAVINGS 有权
    充电泵节电

    公开(公告)号：US20140253180A1

    公开(公告)日：2014-09-11

    申请号：US13785601

    申请日：2013-03-05

    Applicant: QUALCOMM INCORPORATED

    Inventor： Le Wang ,  Vijayakumar Dhanasekaran

    IPC: H03K3/012

    CPC classification number: H02M3/07 ,  H02M2003/071

    Abstract: Exemplary embodiments are directed to systems, devices, methods, and computer-readable media for reducing static and dynamic power consumption of a charge pump. In one embodiment, a device may include a plurality of switches, each switch of the plurality having a gate coupled to a dedicated driver of a plurality of drivers. The device may further include at least one clamp switch coupled to at least one driver of the plurality of drivers and configured to adjust a rail voltage of the at least one driver if an input voltage is greater than a threshold voltage. In another embodiment, the device may include a plurality of multiplexers, each multiplexer of the plurality of multiplexers coupled to a portion of an associated switch of the plurality of switches and configured to disable the portion of the associated switch if a clock frequency of the charge pump is below a threshold frequency.

    Abstract translation: 示例性实施例涉及用于减少电荷泵的静态和动态功耗的系统，设备，方法和计算机可读介质。 在一个实施例中，设备可以包括多个开关，多个开关中的每个开关具有耦合到多个驱动器的专用驱动器的栅极。 该装置还可以包括耦合到多个驱动器中的至少一个驱动器的至少一个钳位开关，并被配置为如果输入电压大于阈值电压则调整至少一个驱动器的轨道电压。 在另一个实施例中，设备可以包括多个多路复用器，多个复用器的每个多路复用器耦合到多个交换机中的相关联的开关的一部分，并且被配置为如果电荷的时钟频率 泵低于阈值频率。

    METHOD AND APPARATUS FOR IMPROVING DEVICE RELIABILITY USING ESTIMATED CURRENT IN A DYNAMIC PROGRAMMABLE SWITCHER DRIVER
    25.
    发明申请
    METHOD AND APPARATUS FOR IMPROVING DEVICE RELIABILITY USING ESTIMATED CURRENT IN A DYNAMIC PROGRAMMABLE SWITCHER DRIVER 审中-公开
    使用动态可编程开关驱动器中的估计电流来提高器件可靠性的方法和装置

    公开(公告)号：US20140232362A1

    公开(公告)日：2014-08-21

    申请号：US13773384

    申请日：2013-02-21

    Applicant: QUALCOMM INCORPORATED

    Inventor： Hanil Lee ,  Vijayakumar Dhanasekaran

    IPC: H02M3/155

    CPC classification number: H02M3/155 ,  H02M2001/0019 ,  H02M2001/0029

    Abstract: A method and apparatus for a dynamic programmable switcher driver using estimated current for device reliability is provided. The method adjusts a rate of closure of an electronic switch and begins when the load current of the Buck regulator is estimated. This estimated current flow is then compared with a predetermined threshold. If the estimated current flow is greater than the predetermined threshold then the rate of closure of the electronic switch is decreased. If the estimated current flow is less than the predetermined threshold then the rate of closure of the switch is increased. An apparatus for adjusting a rate of closure of an electronic switch is also provided. The apparatus includes: an adjustable p-driver having an internal register value; an adjustable n-driver having an internal register value; a positive switch connected to the adjustable p-driver; and a negative switch connected to the adjustable n-driver.

    Abstract translation: 提供了一种使用估计电流进行器件可靠性的动态可编程切换器驱动器的方法和装置。 该方法调节电子开关的闭合速率，并在降压调节器的负载电流进行估计时开始。 然后将该估计电流与预定阈值进行比较。 如果估计的电流大于预定阈值，则电子开关的闭合速率降低。 如果估计的电流小于预定阈值，则开关的闭合速率增加。 还提供了一种用于调节电子开关闭合速率的装置。 该装置包括：具有内部寄存器值的可调节p驱动器; 具有内部寄存器值的可调n驱动器; 连接到可调式p驱动器的正极开关; 以及连接到可调节n驱动器的负极开关。

    Digital-to-analog converter with glitch-irrelevant reference voltage to increase linearity
    27.
    发明授权
    Digital-to-analog converter with glitch-irrelevant reference voltage to increase linearity 有权

    公开(公告)号：US10673449B1

    公开(公告)日：2020-06-02

    申请号：US16398962

    申请日：2019-04-30

    Applicant: QUALCOMM Incorporated

    Inventor： Chien-Chung Yang ,  Dongyang Tang ,  Vijayakumar Dhanasekaran

    IPC: H03M1/06

    Abstract: A digital-to-analog converter has both a plurality of DAC stages and a plurality of dummy stages. Each DAC stage causes a glitch or disturbance to a pair of reference voltages when the DAC stage changes its switching state. Each dummy stage also causes a similar glitch or disturbance to the pair of reference voltages when the dummy stage changes its switching state. The dummy stages are controlled to change their switching state responsive to how many DAC stages change their switching state such that a total glitch induced onto the reference voltages remains substantially constant across a succession of digital words converted by the digital-to-analog converter into an analog output signal.

    Slew rate control boost circuits and methods
    29.
    发明授权
    Slew rate control boost circuits and methods 有权
    压摆率控制升压电路及方法

    公开(公告)号：US09467098B2

    公开(公告)日：2016-10-11

    申请号：US14533928

    申请日：2014-11-05

    Applicant: QUALCOMM Incorporated

    Inventor： Xin Fan ,  Vijayakumar Dhanasekaran

    IPC: H03F3/26 ,  H03F1/32 ,  H03F1/02 ,  H03F3/04

    CPC classification number: H03F1/32 ,  H03F1/0205 ,  H03F1/0266 ,  H03F1/086 ,  H03F1/3217 ,  H03F3/04 ,  H03F3/185 ,  H03F3/3023 ,  H03F2200/03 ,  H03F2200/18 ,  H03F2200/555 ,  H03F2201/3215 ,  H03F2203/30105 ,  H03F2203/45248

    Abstract: The present disclosure amplifier circuits and methods having boosted slew rates. In one embodiment, an amplifier circuit comprises an output stage comprising a first output transistor, the first output transistor comprising a gate, a source, and a drain, wherein the gate receives a signal to be amplified. A bias circuit biases the gate of the first output transistor. A damping circuit is coupled the gate of the first output transistor and is configured to produce a high impedance at low frequencies and a low impedance at high frequencies. The damping circuit includes a current limit circuit to limit current to the gate of the first output transistor when a voltage on the gate of the first output transistor decreases in response to the signal.

    Abstract translation: 本公开的放大器电路和方法具有升压转换速率。 在一个实施例中，放大器电路包括输出级，其包括第一输出晶体管，第一输出晶体管包括栅极，源极和漏极，其中栅极接收待放大的信号。 偏置电路偏置第一输出晶体管的栅极。 阻尼电路耦合第一输出晶体管的栅极，并被配置为在低频下产生高阻抗，在高频下产生低阻抗。 当第一输出晶体管的栅极上的电压响应于该信号而减小时，阻尼电路包括电流限制电路，以限制到第一输出晶体管的栅极的电流。

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