公开(公告)号：US09502088B2

公开(公告)日：2016-11-22

申请号：US14499155

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Sara Choi ,  Jisu Kim ,  Taehui Na ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16 ,  G11C7/14 ,  G11C7/06 ,  G11C7/08 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations.

Abstract translation: 系统和方法涉及提供用于读取电阻式存储器元件的恒定感测电流。 负载电压发生器基于配置为提供与过程电压 - 温度变化不变的恒定电流的电流镜提供负载电压。 基于所产生的负载电压，通过将从恒定电流反射的感测电流通过电阻性存储元件来产生数据电压。 产生参考电压，也可以基于产生的负载电压，并通过将从恒定电流反射的参考电流通过参考单元。 存储在电阻性存储器元件中的逻辑值基于数据电压和参考电压的比较来确定，其中确定不受处理电压 - 温度变化的影响。

公开(公告)号：US09111635B2

公开(公告)日：2015-08-18

申请号：US13869110

申请日：2013-04-24

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Zhongze Wang ,  Choh fei Yeap

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104 ,  Y10T29/41

Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

Abstract translation: 公开了具有读优选单元结构和写驱动器的静态随机存取存储器（SRAM）。 在一个实施例中，SRAM具有六个晶体管位单元。 读优选位单元通过提供两个反相器来实现，每个反相器具有上拉晶体管，下拉晶体管和通过栅极晶体管。 每个上拉晶体管与反馈回路相关联。 反馈环路改善了随机的静态噪声容限。 每个晶体管具有宽度和长度。 传输栅晶体管的长度增加。 下拉晶体管的宽度彼此相等，并且也等于通过栅极晶体管的宽度。 通过栅极和下拉晶体管的宽度也可以相对于现有设计而增加。 也可以使用写辅助电路来提高性能。

公开(公告)号：US10290340B1

公开(公告)日：2019-05-14

申请号：US15939484

申请日：2018-03-29

Applicant: QUALCOMM Incorporated ,  Yonsei University, University-Industry Foundation

Inventor： Seong-Ook Jung ,  Sara Choi ,  Hong Keun Ahn ,  Seung Hyuk Kang ,  Sungryul Kim

IPC: G11C11/16 ,  H01L43/08 ,  G11C7/06

Abstract: Aspects disclosed in the detailed description include offset-canceling (OC) write operation sensing circuits for sensing switching in a magneto-resistive random access memory (MRAM) bit cell in an MRAM for a write operation. The OC write operation sensing circuit is configured to sense when MTJ switching occurs in MRAM bit cell. In an example, the OC write operation sensing circuit includes a voltage sensing circuit and a sense amplifier. The voltage sensing circuit employs a capacitive-coupling effect so that the output voltage drops in response to MTJ switching for both logic ‘0’ and logic ‘1’ write operations. The sense amplifier has a single input and a single output node with an output voltage indicating when MTJ switching has occurred in the MRAM bit cell. A single input transistor and pull-up transistor are provided in the sense amplifier in one example to provide an offset-canceling effect.

公开(公告)号：US09800271B2

公开(公告)日：2017-10-24

申请号：US14852988

申请日：2015-09-14

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Sara Choi ,  Byung Kyu Song ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim ,  Seung Hyuk Kang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/15

CPC classification number: H03M13/616 ,  G06F11/10 ,  G06F11/1012 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/617 ,  H03M13/6502

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

公开(公告)号：US09583178B2

公开(公告)日：2017-02-28

申请号：US13741869

申请日：2013-01-15

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.

Abstract translation: 静态存储单元的方法和装置。 静态存储单元可以包括第一栅极晶体管，其包括第一背栅极节点和包括第二后栅极节点的第二栅极晶体管。 静态存储单元可以包括包括第三后栅极节点的第一下拉晶体管和包括第四背栅极节点的第二下拉晶体管。 第一下拉晶体管的源节点，第二下拉晶体管的源节点以及第一，第二，第三和第四后门节点彼此电耦合以形成公共节点。

公开(公告)号：US09281039B2

公开(公告)日：2016-03-08

申请号：US13953771

申请日：2013-07-30

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Seung H. Kang

IPC: G11C11/15 ,  G11C11/16 ,  H01L43/02

CPC classification number: G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/02

Abstract: An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells.

Abstract translation: 一种装置包括一组数据单元和耦合到该组数据单元的参考单元。 参考单元包括四个磁隧道结（MTJ）单元。

公开(公告)号：US20130215675A1

公开(公告)日：2013-08-22

申请号：US13853146

申请日：2013-03-29

Applicant: Qualcomm Incorporated

Inventor： Kyungho Ryu ,  Jisu Kim ,  Seong-Ook Jung ,  Seung H. Kang

IPC: G11C11/16 ,  H01L43/12

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  H01L43/12 ,  Y10T29/4902

Abstract: In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.

Abstract translation: 在自旋转移力矩磁阻随机存取存储器（STT-MRAM）中，位单元阵列可以具有基本上平行于字线的源极线。 源极线可以基本上垂直于位线。 源极线控制单元包括公共源极线驱动器和被配置为选择各个源极线的源极线选择器。 源极线驱动器和源极线选择器可以以多路复用关系耦合。 位线控制单元包括公共位线驱动器和复用关系的位线选择器。 位线控制单元包括耦合在公共源线驱动器和位线选择线和位线之间的正沟道金属氧化物半导体（PMOS）元件。