公开(公告)号：US10164768B1

公开(公告)日：2018-12-25

申请号：US15904222

申请日：2018-02-23

Applicant: QUALCOMM Incorporated

Inventor： Ravindraraj Ramaraju ,  Rakesh Vattikonda ,  Samrat Sinharoy ,  De Lu ,  Bo Pang

IPC: H04L9/00 ,  H03K19/00

Abstract: In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.

公开(公告)号：US20180174623A1

公开(公告)日：2018-06-21

申请号：US15381587

申请日：2016-12-16

Applicant: QUALCOMM Incorporated

Inventor： Fei Xu ,  Rakesh Vattikonda ,  Dina McKinney ,  Zhen Chen ,  Yun Li ,  Zhenbiao Ma ,  De Lu

IPC: G11C7/10 ,  G06F3/06

CPC classification number: G11C7/1012 ,  G11C7/222

Abstract: An apparatus and method are disclosed for transferring data from a first core to a second core of an integrated circuit (IC). The first core includes first and second memory blocks (e.g., first and second portions of a first-in-first-out (FIFO) memory coupled to first and second pre-multiplexers, respectively). The second core includes a multiplexer including first and second inputs coupled to the first and second memory blocks, respectively. Additionally, the second core includes a read controller configured to generate a first read control signal to cause the first and second memory blocks to transfer data to the first and second inputs of the multiplexer, respectively; and generate a second read control signal to cause the multiplexer to transfer data from the first and inputs to an output of the multiplexer.

公开(公告)号：US20180006651A1

公开(公告)日：2018-01-04

申请号：US15367751

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Rakesh Vattikonda ,  De Lu ,  Ramaprasath Vilangudipitchai ,  Samrat Sinharoy ,  Rui Chen

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K3/356121 ,  H03K3/356191 ,  H03K19/0013 ,  H03K19/01855 ,  H03K19/0963

Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

公开(公告)号：US09536578B2

公开(公告)日：2017-01-03

申请号：US13863989

申请日：2013-04-16

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Changho Jung ,  Sei Seung Yoon ,  Rakesh Vattikonda ,  Nishith Desai

IPC: G11C7/12 ,  G11C7/10 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/419

Abstract: A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.

Abstract translation: 用于存储器电路的写驱动器包括控制电路，该控制电路被配置为：基于第二域中的输入信号，并响应于第一推挽驱动器响应于第一推挽驱动器，在第一节点处的第一电压域中产生第一驱动信号 模式选择信号处于第一模式，其中第一驱动信号处于与输入信号相同的逻辑电平; 操作第二推挽驱动器以基于输入信号在第二节点处的第一电压域中产生第二驱动信号，并且响应于模式选择信号处于第一模式，其中第二驱动信号为补码 相对于输入信号的逻辑电平; 并且响应于所述模式选择信号处于第二模式，操作所述第一和第二推挽驱动器使所述第一和第二节点浮动。

公开(公告)号：US20150303921A1

公开(公告)日：2015-10-22

申请号：US14257212

申请日：2014-04-21

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Frank Guo ,  Rakesh Vattikonda

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/356182

Abstract: A level-shifter is provided with PMOS stacks that are selectively weakened or strengthened depending upon the binary state of an input signal.

Abstract translation: 电平移位器具有根据输入信号的二进制状态选择性地削弱或加强的PMOS堆叠。

公开(公告)号：US20150085554A1

公开(公告)日：2015-03-26

申请号：US14503861

申请日：2014-10-01

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Nishith Desai ,  Rakesh Vattikonda ,  ChangHo Jung ,  Sei Seung Yoon

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

Abstract translation: 静态三元内容可寻址存储器（TCAM）包括密钥单元和耦合到中间匹配行的掩码单元。 关键单元耦合到第一下拉晶体管和第一上拉晶体管。 掩模单元耦合到第二下拉晶体管和第二上拉晶体管。 第一下拉晶体管和第二下拉晶体管并联连接，第一上拉晶体管和第二上拉晶体管串联连接。 匹配线输出还耦合到第一下拉晶体管和第二下拉晶体管，并且还耦合到第一上拉晶体管和第二上拉晶体管。

公开(公告)号：US08976607B2

公开(公告)日：2015-03-10

申请号：US13784830

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Nishith Desai ,  Rakesh Vattikonda ,  Changho Jung

IPC: G11C16/04 ,  G11C7/10 ,  G11C11/417 ,  G11C7/22

CPC classification number: G11C7/1096 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/417 ,  G11C2207/2227

Abstract: Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power. The write driver circuit shifts or adjusts voltage levels between a first voltage domain to a second voltage domain. In one example, the write driver circuit is coupled to a global write bitline and a local write bitline that is coupled to one or more bitcells (of SRAM memory). The write driver circuit converts a first voltage level at the global write bitline to a second voltage level at the local write bitline during a write operation.

Abstract translation: 本文提供了能够在双电压域存储器架构中有效操作的快速，高能量写入驱动器的各个方面。 具体来说，这里描述的写入驱动器的各个方面将高速驱动器与电压电平转换能力相结合，可以在减少使用较低功耗的硅片区域的同时有效地实现。 写驱动器电路移位或调整第一电压域与第二电压域之间的电压电平。 在一个示例中，写驱动器电路耦合到耦合到SRAM存储器的一个或多个位单元的全局写位线和本地写位线。 写入驱动器电路在写操作期间将全局写位线处的第一电压电平转换为本地写位线处的第二电压电平。

公开(公告)号：US08971096B2

公开(公告)日：2015-03-03

申请号：US13953473

申请日：2013-07-29

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Rakesh Vattikonda ,  Nishith Desai ,  Sei Seung Yoon

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16

Abstract: A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.

Abstract translation: 包括一对交叉耦合的反相器的多端口位单元通过在写入操作期间从电源和接地中选择性隔离交叉耦合的反相器中的第一个而提供增加的写入速度和增强的工作电压范围。 写入操作通过写入端口发生，该写入端口包括被配置为将由第一交叉耦合的反相器驱动的第一节点耦合到写入位线的传输门极。 位单元中的剩余的第二交叉耦合反相器被配置为驱动耦合到多个读端口的第二节点。

公开(公告)号：US20140253201A1

公开(公告)日：2014-09-11

申请号：US13787530

申请日：2013-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Changho Jung ,  Nishith Desai ,  Rakesh Vattikonda

IPC: H03K3/012 ,  H03K3/011

CPC classification number: H03K3/356104

Abstract: Various apparatuses and methods are disclosed. The system describes a pulse generator comprising a first stage configured to be powered by a first voltage; and a second stage configured to be powered by a second voltage different from the first voltage, wherein the second stage is further configured to generate a pulse in response to an input to the first stage comprising a trigger and feedback from the second stage.

Abstract translation: 公开了各种装置和方法。 该系统描述了脉冲发生器，其包括被配置为由第一电压供电的第一级; 以及第二级，其被配置为由不同于所述第一电压的第二电压供电，其中所述第二级还被配置为响应于包括来自所述第二级的触发和来自所述第一级的输入而产生脉冲。