公开(公告)号：US10147646B2

公开(公告)日：2018-12-04

申请号：US15811733

申请日：2017-11-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko Karasaki ,  Hidefumi Saeki ,  Atsushi Harikai

IPC: H01L21/78 ,  H01L21/268

Abstract: A manufacturing process of an element chip comprises a preparation step for preparing a substrate, the substrate including first and second streets crossing each other to define a plurality of element regions. Also, it comprises a first shallow-groove formation step for radiating a laser beam along the first streets to form a plurality of first shallow grooves being shallower than a thickness of the substrate, a second shallow-groove formation step for radiating the laser beam along the second streets to form a plurality of second shallow grooves being shallower than a thickness of the substrate, a first groove formation step for radiating the laser beam along the first shallow grooves to form a plurality of first grooves, and a plasma dicing step for etching the substrate along the first grooves and the second shallow grooves by a plasma exposure to dice the substrate into a plurality of element chips.

公开(公告)号：US09911638B2

公开(公告)日：2018-03-06

申请号：US15015934

申请日：2016-02-04

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai ,  Noriyuki Matsubara

IPC: H01L21/683 ,  H01L21/3065 ,  H01L21/78 ,  H01J37/32 ,  H01L21/687

CPC classification number: H01L21/6831 ,  H01J37/32568 ,  H01J37/32697 ,  H01J37/32715 ,  H01L21/3065 ,  H01L21/6833 ,  H01L21/6836 ,  H01L21/68742 ,  H01L21/78 ,  H01L2221/68327

Abstract: A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck mechanism including an electrode portion disposed inside the stage; a support portion which supports the conveyance carrier; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage, the electrostatic chuck mechanism performs an operation of applying a voltage to the electrode portion after contact of an outer circumferential portion of a holding sheet of the conveyance carrier to the stage, the operation including a voltage varying operation of increasing and decreasing an absolute value of the voltage, and the plasma generation unit generates plasma after completion of the voltage varying operation.

公开(公告)号：US12205823B2

公开(公告)日：2025-01-21

申请号：US17550309

申请日：2021-12-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Toshiyuki Takasaki ,  Ryota Furukawa ,  Atsushi Harikai ,  Shogo Okita

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/78

Abstract: Disclosed is a method for producing element chips. The method includes: a preparing step of preparing a substrate 10 that is held on a holding sheet 22 that is supported by a frame 21, the substrate including element regions and dicing regions; a protective film forming step of forming a protective film 15 so as to cover the frame 21, the holding sheet 22, and the substrate 10; a patterning step of removing a part of the protective film 15 so as to expose the dicing regions of the substrate 10; a plasma dicing step including a process that uses a plasma that contains fluorine, the plasma dicing step being a step of individualizing the substrate 10 into a plurality of element chips; and a fluorine removing step of removing, together with the protective film 15, fluorine attached to the protective film 15 in the plasma dicing step.

公开(公告)号：US11682575B2

公开(公告)日：2023-06-20

申请号：US17116008

申请日：2020-12-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita

IPC: H01L21/683 ,  H01L21/3065 ,  H01L21/687 ,  H01J37/32 ,  H01L21/311 ,  H01L21/78

CPC classification number: H01L21/6833 ,  H01J37/32715 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/6836 ,  H01L21/68742 ,  H01L21/78 ,  H01J2237/334 ,  H01L2221/68327

Abstract: A plasma processing apparatus for plasma processing a substrate held on a conveying carrier, the carrier including a holding sheet and a frame supporting an outer periphery of the holding sheet. The apparatus includes a controller that controls a plasma generator, an electrostatic adsorption mechanism, and a lifting system, to sequentially execute: an adsorption step allowing the substrate to be adsorbed electrostatically to a stage; an etching step of exposing the substrate adsorbed electrostatically to the stage to an etching plasma; a frame separation step of lifting the support, to separate the frame away from the stage, with at least part of the holding sheet kept in contact with the stage; a holding sheet separation step of separating the holding sheet away from the stage; and a static elimination step of exposing the substrate separated away from the stage to a static elimination plasma.

公开(公告)号：US20220181188A1

公开(公告)日：2022-06-09

申请号：US17456908

申请日：2021-11-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Akihiro Itou

IPC: H01L21/683 ,  H01L21/3065 ,  H01J37/32

Abstract: A plasma processing method including: a process of placing a work piece on a stage provided in a chamber, the work piece including a substrate and a holding member having an adhesive layer on a surface and holding the substrate via the adhesive layer, and having an exposed portion where the adhesive layer is exposed outside the substrate; and a plasma etching process of etching the substrate with a plasma generated in the chamber, with the exposed portion exposed to the plasma. In response to occurrence of an interruption in the plasma etching process, a cleaning process of exposing a surface of the substrate to a plasma containing an oxidizing gas is performed, and then the plasma etching process is resumed.

公开(公告)号：US11219929B2

公开(公告)日：2022-01-11

申请号：US16896338

申请日：2020-06-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro Itou ,  Atsushi Harikai ,  Toshiyuki Takasaki ,  Hidefumi Saeki ,  Shogo Okita

IPC: B08B3/08 ,  B08B3/04

Abstract: An element chip cleaning method including: an element chip preparation step of preparing at least one element chip having a first surface and a second surface opposite the first surface, the first surface covered with a resin film; a first cleaning step of bringing a first cleaning liquid into contact with the resin film, the first cleaning liquid including a solvent that dissolves at least part of a resin component contained in the resin film; and a second cleaning step of spraying a second cleaning liquid against the resin film from the first surface side of the element chip, after the first cleaning step.

公开(公告)号：US11189480B2

公开(公告)日：2021-11-30

申请号：US16809755

申请日：2020-03-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai ,  Akihiro Itou

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/78 ,  H01L21/463 ,  H01L21/82

Abstract: An element chip manufacturing method including: a preparing step of preparing a substrate including a plurality of element regions and a dicing region defining the element regions, the substrate having a first surface and a second surface opposite the first surface; a laser scribing step of applying a laser beam to the dicing region from a side of the first surface, to form a groove corresponding to the dicing region and being shallower than a thickness of the substrate; a cleaning step of exposing the first surface of the substrate to a first plasma, to remove debris on the groove; and a dicing step of exposing the substrate at a bottom of the groove to a second plasma after the cleaning step, to dice the substrate into element chips including the element regions. The first plasma is generated from a process gas containing a carbon oxide gas.

公开(公告)号：US10796960B2

公开(公告)日：2020-10-06

申请号：US16218554

申请日：2018-12-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi Saeki ,  Atsushi Harikai

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/268 ,  H01L21/304

Abstract: A manufacturing process of an element chip, comprising a substrate preparing step for preparing a substrate having first and second sides opposed to each other, and including a plurality of dicing regions and element regions defined by the dicing regions, the first side being covered by a protective film, a first laser-grooving step for forming a plurality of grooves by irradiating a laser beam to the first side along the dicing regions, and a plasma-dicing step for plasma-etching the substrate along the grooves in depth through a plasma exposure, thereby to dice the substrate into a plurality of element chips, wherein the second side of the substrate and an annular frame are held on a holding sheet in the substrate preparing step, and wherein the laser beam is irradiated only in a region inside an outer edge of the substrate in the first laser-grooving step.

公开(公告)号：US10475704B2

公开(公告)日：2019-11-12

申请号：US15408703

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara ,  Mitsuru Hiroshima ,  Mitsuhiro Okune

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L23/31 ,  H01L23/29

Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into element chips 10 by exposing the substrate to a first plasma. Therefore, element chips having a first surface, a second surface, and a side surface connecting the first surface and the second surface are held spaced from each other on a carrier. A protection film covering the element chip is formed only on the side surface and it is possible to suppress creep-up of a conductive material to the side surface in the mounting step by exposing the element chips to second plasma in which a mixed gas of fluorocarbon and helium is used as a raw material gas.

公开(公告)号：US10297487B2

公开(公告)日：2019-05-21

申请号：US15822568

申请日：2017-11-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai ,  Noriyuki Matsubara ,  Akihiro Itou

IPC: H01L21/683 ,  H01L21/311 ,  H01L21/78 ,  H01L21/304 ,  H01L23/00 ,  H01J37/00 ,  H01L21/67

Abstract: Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.