公开(公告)号：US08994427B2

公开(公告)日：2015-03-31

申请号：US13937424

申请日：2013-07-09

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Baoqing Huang ,  Yan Yan

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract translation: 公开了一种用于占空比失真补偿的方法和装置。 在一个实施例中，集成电路包括具有主数据路径和补偿数据路径的差分信号发送器。 主数据路径包括具有耦合到差分输出的输出端的第一和第二差分驱动器电路。 发送控制器被配置为将数据发送到主和补偿数据路径中，数据对应于顺序发送的比特对，包括奇数数据位，后跟偶数数据位，并进一步被配置为确定各个占空比宽度 由传输控制器接收的奇数和偶数数据位。 传输控制器被配置为使得第一和第二驱动器电路基于其所接收的各自的占空比宽度来均衡发送的奇数和偶数数据位的相应占空比宽度。

公开(公告)号：US20230155867A1

公开(公告)日：2023-05-18

申请号：US18154248

申请日：2023-01-13

Applicant: Oracle International Corporation

Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

IPC: H04L25/03 ,  H04B1/16

CPC classification number: H04L25/03057 ,  H04B1/16

Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

公开(公告)号：US20210135907A1

公开(公告)日：2021-05-06

申请号：US16671146

申请日：2019-10-31

Applicant: Oracle International Corporation

Inventor： Xun Zhang ,  Chaitanya Palusa ,  Dawei Huang ,  Muthukumar Vairavan ,  Jianghui Su

IPC: H04L25/03 ,  H04B1/16

Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

公开(公告)号：US10483952B1

公开(公告)日：2019-11-19

申请号：US15971126

申请日：2018-05-04

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Xun Zhang ,  Muthukumar Vairavan ,  Rajesh Kumar ,  Dawei Huang

IPC: H03K5/007 ,  H03F3/45 ,  H04L25/03 ,  H03G3/30

Abstract: A method and an apparatus for correcting baseline wander is disclosed. The method and apparatus may include receiving a serial data stream that encodes a plurality of data symbols, and determining an average magnitude of a first data value included in one or more data symbols of a subset of the plurality of data symbols, and an average magnitude of a second value included in the one of more data symbols of the subset of the plurality of data symbols. A common mode operating point of an equalizer circuit may be adjusted using the average magnitude of the first data value and the average magnitude of the second data value.

公开(公告)号：US20190341914A1

公开(公告)日：2019-11-07

申请号：US15971126

申请日：2018-05-04

Applicant: Oracle International Corporation

Inventor： Jianghui Su ,  Xun Zhang ,  Muthukumar Vairavan ,  Rajesh Kumar ,  Dawei Huang

IPC: H03K5/007 ,  H03F3/45 ,  H03G3/30 ,  H04L25/03

Abstract: A method and an apparatus for correcting baseline wander is disclosed. The method and apparatus may include receiving a serial data stream that encodes a plurality of data symbols, and determining an average magnitude of a first data value included in one or more data symbols of a subset of the plurality of data symbols, and an average magnitude of a second value included in the one of more data symbols of the subset of the plurality of data symbols. A common mode operating point of an equalizer circuit may be adjusted using the average magnitude of the first data value and the average magnitude of the second data value.

公开(公告)号：US10142089B2

公开(公告)日：2018-11-27

申请号：US15466469

申请日：2017-03-22

Applicant: Oracle International Corporation

Inventor： Yuhan Yao ,  Xun Zhang ,  Dawei Huang ,  Jianghui Su ,  Muthukumar Vairavan ,  Chaitanya Palusa

IPC: H04L7/00 ,  H04L7/02 ,  H04B1/16 ,  H03L7/08

Abstract: Embodiments include systems and methods for improving link performance and tracking capability of a baud-rate clock data recovery (CDR) system using transition pattern detection. For example, a multi-level signal is received via a data channel and converted to a pseudo-NRZ signal. CDR early/late voting can be derived from the converted (baud-rate) pseudo-NRZ signal and from error signals from the received PAM4 signal, and the voting can be implemented with different phase error detector (PED) functional approaches. Different approaches can yield different CDR performance characteristics and can tend to favor different PAM4 transition patterns. Embodiments can identify jittery patterns for a particular CDR implementation and can add features to the CDR to filter out those patterns from being used for CDR early/late voting.

公开(公告)号：US20140215245A1

公开(公告)日：2014-07-31

申请号：US13753130

申请日：2013-01-29

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Hongtao Zhang ,  Da-wei Huang ,  Jianghui Su

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  H04L12/6418

Abstract: Systems and methods for reducing power consumption of systems using serialized data transmission. In a multi-node system, the reiterative steps for the setup of the lanes within links between the nodes produces both a time invariant set of parameters associated with the channel properties of the lanes and a time variant set of parameters associated with receiver clock alignment. The time invariant set is stored in persistent storage. Links may be turned on and turned off. When a link is turned on again, the stored time invariant set may be used as initial values to reconfigure both the time invariant and the time variant sets, thereby greatly reducing the delay to begin using the link again. The reduced delay may significantly speed up the wakening process for the links, thereby encouraging the use of low-power techniques that include tuning off lanes.

Abstract translation: 使用串行数据传输降低系统功耗的系统和方法。 在多节点系统中，用于在节点之间的链路内建立通道的重复步骤产生与通道的通道属性相关联的时间不变量参数和与接收器时钟对准相关联的参数的时变集合。 时间不变集存储在持久存储器中。 链接可能会打开并关闭。 当再次打开链接时，可以将所存储的时间不变集合用作初始值以重新配置时间不变集合和时间变量集合，从而大大减少开始再次使用链接的延迟。 减少的延迟可能会显着加速链路的唤醒过程，从而鼓励使用包括调整车道的低功率技术。