公开(公告)号：US20200249328A1

公开(公告)日：2020-08-06

申请号：US16267162

申请日：2019-02-04

Applicant: OmniVision Technologies, Inc.

Inventor： Eric A. G. Webster

IPC: G01S7/486 ,  G01S17/89 ,  G01S17/42 ,  G01S7/481 ,  G01S7/497

Abstract: A time-of-flight (TOF) pixel includes a semiconductor material and a photogate disposed proximate to a frontside of the semiconductor material. The photogate is positioned to transfer charge in the semiconductor material toward the frontside in response to a voltage applied to the photogate. A floating diffusion is disposed in the semiconductor material proximate to the frontside of the semiconductor material, and one or more virtual phase implants is disposed in the semiconductor material proximate to the frontside of the semiconductor material. At least one of the one or more virtual phase implants extend laterally from under the photogate to the floating diffusion to transfer the charge to the floating diffusion.

公开(公告)号：US10681295B2

公开(公告)日：2020-06-09

申请号：US15798067

申请日：2017-10-30

Applicant: OmniVision Technologies, Inc.

Inventor： Eric A. G. Webster

IPC: H04N5/378 ,  G01S17/10 ,  G01S17/89 ,  H04N5/369 ,  G01S7/4865 ,  G06T7/521

Abstract: A time of flight camera includes a light source, a first pixel, a time-to-digital converting, and a controller. The light source is configured to emit light towards an object to be reflected back to the time of flight camera as image light. The first pixel includes a photodetector to detect the image light and to convert the image light into an electric signal. The time-to-digital converter is configured to generate timing signals representative of when the light source emits the light and when the photodetector detects the image light. The controller is coupled to the light source, the first pixel, and the time-to-digital converter. The controller includes logic that when executed causes the time of flight camera to perform operations. The operations include determining a detection window for a round-trip time of the image light based, at least in part, on the timing signals and first pulses of the light. The operations also include determining the round-trip time based, at least in part, on the timing signals and second pulses of the light detected within the detection window.

公开(公告)号：US20190324126A1

公开(公告)日：2019-10-24

申请号：US15958364

申请日：2018-04-20

Applicant: OmniVision Technologies, Inc.

Inventor： Olivier Bulteel ,  Eric A. G. Webster ,  Lindsay Grant

IPC: G01S7/486 ,  G01S17/36 ,  G01S7/497 ,  G01S7/491

Abstract: A time-of-flight (TOF) sensor includes a light source structured to emit light and a plurality of avalanche photodiodes. The TOF sensor also includes a plurality of pulse generators, where individual pulse generators are coupled to individual avalanche photodiodes in the plurality of avalanche photodiodes. Control circuitry is coupled to the light source, the plurality of avalanche photodiodes, and the plurality of pulse generators, to perform operations. Operations may include emitting the light from the light source, and receiving the light reflected from an object with the plurality of avalanche photodiodes. In response to receiving the light with the plurality of avalanche photodiodes, a plurality of pulses may be output from the individual pulse generators corresponding to the individual photodiodes that received the light. And, in response to outputting the plurality of pulses, a timing signal may be output when the plurality of pulses overlap temporally.

公开(公告)号：US10062722B2

公开(公告)日：2018-08-28

申请号：US15284961

申请日：2016-10-04

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sohei Manabe ,  Keiji Mabuchi ,  Takayuki Goto ,  Vincent Venezia ,  Boyd Albert Fowler ,  Eric A. G. Webster

IPC: H01L27/148 ,  H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469

Abstract: An image sensor includes a pixel array having plurality of pixel cells arranged into a plurality of rows and a plurality of columns of pixel cells in a first semiconductor die. A plurality of pixel support circuits are arranged in a second semiconductor die that is stacked and coupled together with the first semiconductor die. A plurality of interconnect lines are coupled between the first and second semiconductor dies, and each one of the plurality of pixel cells is coupled to a corresponding one of the plurality of pixel support circuits through a corresponding one plurality of interconnect lines. A plurality of shield bumps are disposed proximate to corners of the pixel cells in the pixel array and between the first and second semiconductor dies such that each one of the plurality of shield bumps is disposed between adjacent interconnect lines along a diagonal of the pixel array.

公开(公告)号：US09825073B2

公开(公告)日：2017-11-21

申请号：US14286478

申请日：2014-05-23

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster

IPC: H01L27/146 ,  H04N5/378

CPC classification number: H01L27/14605 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14649 ,  H04N5/378

Abstract: An image sensor includes a photodiode disposed in semiconductor material to accumulate image charge in response to light directed through a back side of the semiconductor material. A scattering structure is disposed proximate to the front side of the semiconductor material such that the light that is directed into the semiconductor material through the back side is scattered back through the photodiode. A deep trench isolation structure is disposed in the semiconductor material that isolates the photodiode and defines an optical path such that the light that is scattered back through the photodiode in the optical path is totally internally reflected by the DTI. An antireflective coating is disposed on the back side of the semiconductor material and totally internally reflects the light scattered by the scattering structure to confine the light to remain in the optical path until it is absorbed.

公开(公告)号：US20170256666A1

公开(公告)日：2017-09-07

申请号：US15599267

申请日：2017-05-18

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster

IPC: H01L31/107 ,  H04N5/369 ,  H01L27/146 ,  H04N5/33 ,  H01L31/02 ,  H01L31/0232

CPC classification number: H01L31/1075 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/1465 ,  H01L31/02027 ,  H01L31/02327 ,  H04N5/332 ,  H04N5/369

Abstract: An imaging sensor system includes a pixel array having a plurality of pixel cells disposed in a first semiconductor layer, where each one of the plurality of pixel cells has a single photon avalanche diode (SPAD) disposed proximate to a front side of a first semiconductor layer. Each of the plurality of pixel cells includes a guard ring disposed in the first semiconductor layer in a guard ring region proximate to the SPAD, and also includes a guard ring region reflecting structure disposed in the guard ring region proximate to the guard ring and proximate to the front side of the first semiconductor layer. The imaging sensor system also includes control circuitry coupled to the pixel array to control operation of the pixel array, and readout circuitry coupled to the pixel array to readout image data from the plurality of pixel cells.

公开(公告)号：US09419044B2

公开(公告)日：2016-08-16

申请号：US14255535

申请日：2014-04-17

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Dajiang Yang ,  Gang Chen ,  Zhenhong Fu ,  Duli Mao ,  Eric A. G. Webster ,  Sing-Chung Hu ,  Dyson H. Tai

IPC: H01L27/00 ,  H01J40/14 ,  H01L27/146 ,  H01L21/00 ,  H01L31/18 ,  H01L27/148

CPC classification number: H01L27/14643 ,  H01L27/14612 ,  H01L27/14614 ,  H01L27/14689

Abstract: A pixel cell includes a storage transistor disposed in a semiconductor substrate. The storage transistor includes a storage gate disposed over the semiconductor substrate, and a storage gate implant that is annealed and has a gradient profile in the semiconductor substrate under the storage transistor gate to store image charge accumulated by a photodiode disposed in the semiconductor substrate. A transfer transistor is disposed in the semiconductor substrate and is coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor. The transfer transistor includes a transfer gate disposed over the semiconductor substrate. An output transistor is coupled to an output of the storage transistor to selectively transfer the image charge from the storage transistor to a read out node. The output transistor includes an output gate disposed over the semiconductor substrate.

Abstract translation: 像素单元包括设置在半导体衬底中的存储晶体管。 存储晶体管包括设置在半导体衬底上的存储栅极，以及在存储晶体管栅极下的半导体衬底中退火并具有梯度分布的存储栅极注入，以存储由设置在半导体衬底中的光电二极管累积的图像电荷。 传输晶体管设置在半导体衬底中并耦合在光电二极管和存储晶体管的输入端之间，以选择性地将图像电荷从光电二极管转移到存储晶体管。 转移晶体管包括设置在半导体衬底上的转移栅极。 输出晶体管耦合到存储晶体管的输出，以选择性地将图像电荷从存储晶体管传送到读出节点。 输出晶体管包括设置在半导体衬底上的输出门。

公开(公告)号：US09331116B2

公开(公告)日：2016-05-03

申请号：US14156053

申请日：2014-01-15

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636

Abstract: A single photon avalanche diode (SPAD) includes an n doped epitaxial layer disposed in a first semiconductor layer. A p doped epitaxial layer is above the n doped epitaxial layer on a back side of the first semiconductor layer. A multiplication junction is defined at an interface between the n doped epitaxial layer and the p doped epitaxial layer. A multiplication junction is reversed biased above a breakdown voltage such that a photon received through the back side of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction. A p− doped guard ring region is implanted in the n doped epitaxial layer surrounding the multiplication junction.

Abstract translation: 单光子雪崩二极管（SPAD）包括设置在第一半导体层中的n掺杂外延层。 p掺杂的外延层在第一半导体层的背面上的n掺杂的外延层之上。 在n掺杂外延层和p掺杂外延层之间的界面处限定一个乘法结。 乘法结被反向偏置在击穿电压之上，使得通过第一半导体层的背面接收的光子在乘法结中触发雪崩倍增处理。 p掺杂的保护环区域被注入围绕乘法结的n掺杂外延层中。

公开(公告)号：US09299732B2

公开(公告)日：2016-03-29

申请号：US14065275

申请日：2013-10-28

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster ,  Tiejun Dai

IPC: H01J40/14 ,  H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14643 ,  H04N5/369 ,  H04N5/37455 ,  H04N5/378

Abstract: An example imaging sensor system includes a Single-Photon Avalanche Diode (SPAD) imaging array formed in a first semiconductor layer of a first wafer. The SPAD imaging array includes an N number of pixels, each including a SPAD region formed in a front side of the first semiconductor layer. The first wafer is bonded to a second wafer at a bonding interface between a first interconnect layer of the first wafer and the second interconnect layer of the second wafer. An N number of digital counters are formed in a second semiconductor layer of the second wafer. Each of the digital counters are configured to count output pulses generated by a respective SPAD region.

Abstract translation: 示例性成像传感器系统包括形成在第一晶片的第一半导体层中的单光子雪崩二极管（SPAD）成像阵列。 SPAD成像阵列包括N个像素，每个像素包括形成在第一半导体层的前侧的SPAD区域。 第一晶片在第一晶片的第一互连层和第二晶片的第二互连层之间的接合界面处接合到第二晶片。 N个数字计数器形成在第二晶片的第二半导体层中。 每个数字计数器被配置为对相应SPAD区域产生的输出脉冲进行计数。

公开(公告)号：US20160027837A1

公开(公告)日：2016-01-28

申请号：US14341257

申请日：2014-07-25

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster ,  Howard E. Rhodes ,  Dominic Massetti

IPC: H01L27/146 ,  H01L31/028

CPC classification number: H01L27/14645 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14649 ,  H01L27/14652 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/028

Abstract: A pixel array including an SixGey layer disposed on a first semiconductor layer. A plurality of pixels is disposed in the first semiconductor layer. The plurality of pixels includes: (1) a first portion of pixels separated from the SixGey layer by a spacer region and (2) a second portion of pixels including a first doped region in contact with the SixGey layer. The pixel array also includes pinning wells disposed between individual pixels in the plurality of pixels. A first portion of the pinning wells extend through the first semiconductor layer. A second portion of the pinning wells extend through the first semiconductor layer and the SixGey layer.

Abstract translation: 包括设置在第一半导体层上的SixGey层的像素阵列。 多个像素设置在第一半导体层中。 多个像素包括：（1）通过间隔区域与SixGey层分离的像素的第一部分和（2）包括与SixGey层接触的第一掺杂区域的像素的第二部分。 像素阵列还包括设置在多个像素中的各个像素之间的钉扎阱。 钉扎井的第一部分延伸穿过第一半导体层。 钉扎阱的第二部分延伸穿过第一半导体层和SixGey层。