公开(公告)号：US11482419B2

公开(公告)日：2022-10-25

申请号：US17106626

申请日：2020-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jhen-Yu Tsai ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L21/265 ,  H01L29/66 ,  H01L29/10

Abstract: The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.

公开(公告)号：US11437481B2

公开(公告)日：2022-09-06

申请号：US16916696

申请日：2020-06-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu

IPC: H01L29/423 ,  H01L27/108 ,  H01L21/8234 ,  H01L27/088

Abstract: The present disclosure provides a semiconductor device with a T-shaped buried gate electrode and a method for forming the semiconductor device. The semiconductor device includes a semiconductor substrate having an active region, and a first gate electrode disposed in the semiconductor substrate. The semiconductor device also includes a first source/drain region and a second source/drain region disposed in the active region and at opposite sides of the first gate electrode. The first gate electrode has a first portion extending across the active region and a second portion extending into the first source/drain region.

公开(公告)号：US20220157824A1

公开(公告)日：2022-05-19

申请号：US17098033

申请日：2020-11-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tseng-Fu Lu

IPC: H01L27/108 ,  G11C5/06

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a storage capacitor, an access transistor, and at least one conductive feature for electrically coupling the storage capacitor to the access transistor. The substrate includes at least one isolation feature defining a plurality of active regions, wherein a plurality of impurity regions of the access transistor are in the active region. The storage capacitor is disposed over the substrate, and the conductive feature extends from the storage capacitor and into a portion of the substrate where one of the impurity regions is disposed. As a result, a contact area between the access transistor and the conductive feature is increased, and an operation speed of the compact semiconductor device is increased.

公开(公告)号：US10825931B2

公开(公告)日：2020-11-03

申请号：US15894954

申请日：2018-02-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L27/108 ,  H01L21/762 ,  H01L21/3065

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.

公开(公告)号：US10818800B2

公开(公告)日：2020-10-27

申请号：US15894580

申请日：2018-02-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Cheng-Hsien Hsieh ,  Tseng-Fu Lu ,  Jhen-Yu Tsai ,  Ching-Chia Huang ,  Wei-Ming Liao

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: The present disclosure provides a semiconductor structure including a substrate, a bottom gate portion disposed in the substrate, a top gate portion stacked over the bottom gate portion, a first channel layer sandwiched between the top gate portion and the bottom gate portion, and a source/drain region disposed in the substrate at two opposite sides of the top gate portion.

公开(公告)号：US10763212B1

公开(公告)日：2020-09-01

申请号：US16388314

申请日：2019-04-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Cheng-Hsien Hsieh ,  Ching-Chia Huang ,  Chen-Lun Ting ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L23/532 ,  H01L27/108 ,  H01L23/528

Abstract: A semiconductor structure includes a substrate including a surface, a first doped region and a second doped region, wherein the first doped region and the second doped region are disposed under the surface; a gate structure disposed between the first doped region and the second doped region; a capacitor disposed over and electrically connected to the first doped region; and a bit line disposed over and electrically connected to the second doped region, wherein the bit line includes a conductive portion and an insulating portion surrounding the conductive portion, and the insulating portion includes ferroelectric material.

公开(公告)号：US10580765B1

公开(公告)日：2020-03-03

申请号：US16207185

申请日：2018-12-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Fang-Wen Liu ,  Tseng-Fu Lu

IPC: H01L27/02 ,  H01L27/06

Abstract: A semiconductor structure includes a silicon control rectifier (SCR) region and a NPN region adjacent to the SCR region. The silicon control rectifier (SCR) region includes a first p-well region, a first n-well region surrounded by the first p-well region and a first P+ region in the first p-well region and spaced apart from the first n-well region. The NPN region includes a second p-well region, a first N+ region, a second N+ region and a second P+ region. The first N+ region is coupled to the second p-well region and an electrostatic discharge source. The second N+ region is coupled to the second p-well region and spaced apart from the first N+ region. The second P+ region is disposed in the second p-well region and equipotentially connected to the first P+ region in the first p-well region.

公开(公告)号：US10559661B2

公开(公告)日：2020-02-11

申请号：US15866888

申请日：2018-01-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jhen-Yu Tsai ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06

Abstract: The present disclosure provides a transistor device and a semiconductor layout structure. The transistor device includes an active region disposed in a substrate, a gate structure disposed over the active region, and a source/drain region disposed at two opposite sides of the gate structure. The active region includes a first region including a first length, a second region including a second length less than the first length, and a third region between the first region and the second region. The gate structure includes a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction. The first portion is disposed over at least the third region of the active region, and the second portion is disposed over at least a portion of the third region and a portion of the second region.

公开(公告)号：US10418356B2

公开(公告)日：2019-09-17

申请号：US15957425

申请日：2018-04-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Fang-Wen Liu ,  Tseng-Fu Lu

IPC: H01L21/70 ,  H01L27/02 ,  H01L29/06 ,  H01L27/08

Abstract: The present disclosure provides a diode structure and an electrostatic discharge (ESD) protection circuit including the same. The diode structure includes a P-type substrate. The diode structure further includes a plurality of wavy N-doping regions formed on the P-type substrate. Each of the wavy N-doping regions extends in a first direction and has an N-doping width in a second direction perpendicular to the first direction. The diode structure further includes a plurality of wavy P-doping regions formed on the P-type substrate. Each of the wavy P-doping regions extends in the first direction and has a P-doping width in the second direction. The N-doping widths are essentially identical at different positions along the first direction, and the P-doping widths are essentially identical at different positions along the first direction.

公开(公告)号：US10381351B2

公开(公告)日：2019-08-13

申请号：US15879929

申请日：2018-01-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/76 ,  H01L27/108 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

Abstract: The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.