公开(公告)号：US10068822B2

公开(公告)日：2018-09-04

申请号：US15281100

申请日：2016-09-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L21/48 ,  H01L23/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A method for forming semiconductor packages includes disposing at least one flow hindering supporter onto a substrate, in which the substrate has at least one active region and at least one gap region surrounded the active region, the flow hindering supporter is located on the gap region; subsequently, disposing at least one die structure onto the active region of the substrate respectively; and then injecting a molding compound flowed into the gap region, to mold the flow hindering supporter and the die structure with the molding compound.

公开(公告)号：US10050021B1

公开(公告)日：2018-08-14

申请号：US15434569

申请日：2017-02-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

Abstract: A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the interconnect feature is in contact with a substrate in the die; and a bump, independent of the die, configured for electrical connection of the active layer.

公开(公告)号：US09991215B1

公开(公告)日：2018-06-05

申请号：US15410430

申请日：2017-01-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/58 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L23/481 ,  H01L24/14

Abstract: A semiconductor structure includes a substrate including a first side and a second side opposite to the first side; a first via extending through the substrate; a second via extending through the substrate; and a metallic structure disposed between the first via and the second via, wherein the first via is isolated from the second via by the metallic structure, the first via and the second via are configured to connect to a signal source or transmit a signal, and the metallic structure is configured to connect to a power or a ground.

公开(公告)号：US09960146B1

公开(公告)日：2018-05-01

申请号：US15462906

申请日：2017-03-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/02 ,  H01L21/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2731 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/92143 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor structure includes a first stacking interposer. The first stacking interposer includes a first interposer having a first surface and a second surface opposite thereto; a plurality of first conductive pillars penetrating through the first interposer from the first surface to the second surface; a plurality of first bumps disposed at a side of the first surface of the first interposer and electrically connected to the first conductive pillars; and a first redistribution layer disposed on the second surface of the first interposer. The first surface has a clearance region where is free of the first bumps. A first chip is disposed over the first redistribution layer. The first chip is aligned with the clearance region of the first surface of the first interposer in a direction perpendicular to the first surface. A plurality of second bumps interconnecting the first redistribution layer with the first chip.

公开(公告)号：US09893037B1

公开(公告)日：2018-02-13

申请号：US15493096

申请日：2017-04-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/06 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/16012 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06593

Abstract: A semiconductor chip includes a semiconductor device with an upper surface and a lower surface opposite to the upper surface. The semiconductor device includes an input terminal, a plurality of through silicon vias, a plurality of selection pads, a plurality of tilt pads and a plurality of tilt conductive structures. The through silicon vias are extended through the semiconductor device. The selection pads are located on the lower surface The tilt pads are located on the upper surface and connected to the selection pads through the through silicon vias respectively. Each tilt pad includes a pad surface that is non-parallel to the upper surface. A lower end of each tilt conductive structure is in contact with the pad surface of each tilt pad, and an upper end of each tilt conductive structure is vertically overlapped with an immediately-adjacent one of the tilt pads.

公开(公告)号：US09711442B1

公开(公告)日：2017-07-18

申请号：US15245200

申请日：2016-08-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/12 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor structure is provided. The semiconductor structure includes an electronic component and a board structure. The board structure includes a dielectric layer structure and at least one elastomer. The dielectric layer structure has a mount region and a peripheral region surrounding the mount region. The electronic component is disposed on the mount region, and the peripheral region has at least one first through hole. The elastomer is disposed in the first through hole.

公开(公告)号：US09664852B1

公开(公告)日：2017-05-30

申请号：US15281102

申请日：2016-09-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: G02B6/10 ,  G02B6/122 ,  H01P3/12 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B2006/12038 ,  G02B2006/12061 ,  H01P3/122

Abstract: A waveguide including a substrate, a plurality of cladding layers, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The cladding layers are present on the substrate and define at least one tunnel therein, in which at least one of the cladding layers is made of metal. The first dielectric layer is disposed in the tunnel and has a first refractive index N1. The second dielectric layer is disposed in the tunnel and has a second refractive index N2. The third dielectric layer is disposed in the tunnel and has a third refractive index N3, and N2>N1 and N2>N3, in which the second dielectric layer is present between the first and third dielectric layers.

公开(公告)号：US09508673B2

公开(公告)日：2016-11-29

申请号：US15143227

申请日：2016-04-29

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  B23K20/00 ,  B23K20/233

CPC classification number: H01L24/48 ,  B23K20/007 ,  B23K20/233 ,  B23K2101/42 ,  B23K2103/08 ,  B23K2103/12 ,  H01L24/45 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48464 ,  H01L2224/48482 ,  H01L2224/73265 ,  H01L2224/78268 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85186 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2924/2076 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is formed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad.

Abstract translation: 引线键合方法包括以下步骤。 首先，提供包括至少一个金属指的基板。 接下来，在基板上设置包括至少一个第一编码焊盘的第一芯片。 接下来，在相应的金属指状物上形成金属球凸块。 接下来，从金属球凸块朝向相应的第一编织垫形成第一线。 接下来，通过电子熄火处理在第一线上形成第一自由空气球。 然后，连接到第一线的第一自由空气球被压在相应的第一编织垫上，使得第一线位于第一自由球和相应的第一编织垫之间。

公开(公告)号：US09147642B2

公开(公告)日：2015-09-29

申请号：US14067989

申请日：2013-10-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a substrate, at least one transistor, at least one metal layer, a conductive pillar, and a connecting structure. The substrate has at least one via passing therethrough. The transistor is at least partially disposed in the substrate. The metal layer is disposed on or above the substrate. The conductive pillar is disposed in the via. The connecting structure is at least partially disposed in the via and connecting the conductive pillar and the metal layer. At least a first portion of the connecting structure is made of a stress releasing material having a coefficient of thermal expansion less than a coefficient of thermal expansion of the conductive pillar. A projection of the transistor in the via overlaps with the connecting structure.

Abstract translation: 集成电路器件包括衬底，至少一个晶体管，至少一个金属层，导电柱和连接结构。 衬底具有穿过其中的至少一个通孔。 晶体管至少部分地设置在衬底中。 金属层设置在基板上或上方。 导电柱设置在通孔中。 连接结构至少部分地布置在通孔中并连接导电柱和金属层。 连接结构的至少第一部分由具有小于导电柱的热膨胀系数的热膨胀系数的应力释放材料制成。 晶体管在通孔中的突起与连接结构重叠。

公开(公告)号：US10923455B2

公开(公告)日：2021-02-16

申请号：US16209540

申请日：2018-12-04

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/324 ,  H01L21/306

Abstract: The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.