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    Memory architecture for layered low-density parity-check decoder
    21.
    发明授权
    Memory architecture for layered low-density parity-check decoder 有权
    分层低密度奇偶校验解码器的内存架构

    公开(公告)号：US09037952B2

    公开(公告)日：2015-05-19

    申请号：US13760609

    申请日：2013-02-06

    Applicant: LSI Corporation

    Inventor： Zongwang Li ,  Yang Han ,  Kaichi Zhang ,  Chung-Li Wang

    IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/27

    CPC classification number: G06F11/10 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/2707 ,  H03M13/6505 ,  H03M13/6566

    Abstract: A hard decision memory interacts with a multi-layered low-density parity-check decoder by sending multiple L values and E values to a multi-layered low-density parity-check decoder (LDPC), and the L value E value hard decision memory (LE hard decision memory) receives one or more hard decisions. The LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements. The use of the LE hard decision memory results improved multi-level LDPC decoding of an LDPC encoded message.

    Abstract translation: 硬判决存储器通过向多层低密度奇偶校验解码器（LDPC）发送多个L值和E值与多层低密度奇偶校验解码器相互作用，并且L值E值硬判决存储器 （LE硬决策存储器）接收一个或多个硬判决。 LE硬判决存储器包括全局映射元件，用于交织来自第一和第二循环的L值，并将交织的值存储在第一存储器元件中。 然后，低密度奇偶校验解码器处理来自第一存储器元件的循环并将输出存储在第二存储元件中。 LE硬决策存储器不包括任何多路复用单元。 LE硬判决存储器的使用结果改进了LDPC编码消息的多级LDPC解码。

    Efficient way to construct LDPC code by comparing error events using a voting based method
    22.
    发明授权
    Efficient way to construct LDPC code by comparing error events using a voting based method 有权
    通过使用基于投票的方法比较错误事件来构建LDPC码的有效方式

    公开(公告)号：US08977925B2

    公开(公告)日：2015-03-10

    申请号：US13743381

    申请日：2013-01-17

    Applicant: LSI Corporation

    Inventor： Denis Vladimirovich Zaytsev ,  Denis Vasilievich Parfenov ,  Yang Han ,  Ivan Leonidovich Mazurenko ,  Dmitry Nicolaevich Babin

    IPC: H03M13/00 ,  H03M13/37 ,  H03M13/11

    CPC classification number: H03M13/3738 ,  H03M13/09 ,  H03M13/1142

    Abstract: A method for ordering trapping sets to find one or more dominant trapping sets includes analyzing a trapping set and a random set of codewords to generate a distance value for each trapping set, and ordering the trapping sets by the distance value. Distance values may be determined for each trapping set by tracking a vote count wherein a correct decode at a certain noise level produces a “right” vote and an incorrect decode at a certain noise level produces a “left” vote. A certain threshold number of “left” votes terminates processing at that noise level.

    Abstract translation: 用于排序陷阱集合以找到一个或多个主要捕获集合的方法包括分析陷阱集合和随机的码字集合以生成每个陷阱集合的距离值，并且将陷阱集合排序距离值。 可以通过跟踪投票计数来确定每个陷阱集合的距离值，其中在某一噪声级别的正确解码产生“正确”投票，并且在某一噪声电平处产生不正确的解码产生“左”投票。 一定数量的“左”选票终止在该噪声级别的处理。

    Systems and methods for distributed low density parity check decoding
    23.
    发明授权
    Systems and methods for distributed low density parity check decoding 有权
    分布式低密度奇偶校验解码的系统和方法

    公开(公告)号：US08930792B2

    公开(公告)日：2015-01-06

    申请号：US13766891

    申请日：2013-02-14

    Applicant: LSI Corporation

    Inventor： Shu Li ,  Shaohua Yang ,  Zongwang Li ,  Yang Han

    IPC: H03M13/00 ,  H03M13/13 ,  H03M13/29 ,  G11B20/18 ,  H04L1/00

    CPC classification number: H03M13/13 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1117 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/2978 ,  H03M13/6325 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. In some cases the systems include a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit. The common circuit is operable to: shift a combination of both a first sub-message from the first data decoder engine and the second sub-message from the second data decoder engine to yield an shifted output, and disaggregate the shifted output to yield a third sub-message to the first data decoder engine and a fourth sub-message to the second decoder engine.

    Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于利用多个数据流进行数据从存储设备的数据恢复的系统和方法。 在一些情况下，系统包括低密度奇偶校验数据解码器电路，其包括至少第一数据解码器引擎和第二数据解码器引擎，每个电耦合到公共电路。 公共电路可操作用于：将来自第一数据解码器引擎的第一子消息和来自第二数据解码器引擎的第二子消息的组合移位以产生移位的输出，并且分解转移的输出以产生第三 子消息发送到第一数据解码器引擎，第四子消息发送到第二解码器引擎。

    DIVERSITY LOOP DETECTOR WITH COMPONENT DETECTOR SWITCHING
    25.
    发明申请
    DIVERSITY LOOP DETECTOR WITH COMPONENT DETECTOR SWITCHING 有权
    多样性环路检测器与组件检测器切换

    公开(公告)号：US20140200849A1

    公开(公告)日：2014-07-17

    申请号：US13741482

    申请日：2013-01-15

    Applicant: LSI CORPORATION

    Inventor： Yang Han ,  Yu Kou ,  Xuebin Wu ,  Bruce A. Wilson

    IPC: G06F17/18

    CPC classification number: H03M13/41

    Abstract: Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset.

    Abstract translation: 本公开的方面涉及用于为分集环路检测器提供分量检测器切换的系统和方法。 通过周期状态似然重置处理，基于斜率的切换处理或交叉连接处理之一来执行分量检测器之间的切换。 联合决策电路在组件检测器之间切换，以通过存在恒定或过渡相位偏移来促进改进的性能。

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