公开(公告)号：US06288956B1

公开(公告)日：2001-09-11

申请号：US09477717

申请日：2000-01-05

Applicant: Tetsushi Tanizaki ,  Tetsuo Kato ,  Mikio Asakura ,  Yasuhiro Konishi ,  Takayuki Miyamoto

Inventor： Tetsushi Tanizaki ,  Tetsuo Kato ,  Mikio Asakura ,  Yasuhiro Konishi ,  Takayuki Miyamoto

IPC: G11C1140

CPC classification number: G11C29/46

Abstract: A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test mode signals are held in the latch circuits. Each test mode circuit further includes decode circuits outputting a group reset signal for resetting a corresponding latch circuit. Thus, a plurality of test mode signals can be combined arbitrarily and serially.

Abstract translation: 根据本发明的半导体器件包括多个测试模式电路。 每个测试模式电路包括解码输入信号和多个锁存电路的多个解码电路。 每个解码电路产生测试模式信号。 测试模式信号保持在锁存电路中。 每个测试模式电路还包括输出用于复位相应的锁存电路的组复位信号的解码电路。 因此，多个测试模式信号可以任意和连续地组合。

公开(公告)号：US5818768A

公开(公告)日：1998-10-06

申请号：US767496

申请日：1996-12-16

Applicant: Seiji Sawada ,  Yasuhiro Konishi

Inventor： Seiji Sawada ,  Yasuhiro Konishi

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC classification number: G11C7/22 ,  G11C7/1045

Abstract: A correspondence defining circuit changes a correspondence between an external signal and an internal signal and supplies it to a mode designating signal generating circuit according to a logic state of an operation mode switching signal. The mode designating signal generating circuit activates a mode designating signal which designates a specific operation mode in a semiconductor device when the internal signal satisfies a prescribed condition. An operation mode setting circuit, applicable to applications in which states of external signals are different without a change of its internal structure, is thus provided.

Abstract translation: 对应定义电路改变外部信号和内部信号之间的对应关系，并根据操作模式切换信号的逻辑状态将其提供给模式指定信号发生电路。 当内部信号满足规定条件时，模式指定信号发生电路激活指定半导体器件中的特定操作模式的模式指定信号。 因此，提供了适用于其外部信号的状态不同而不改变其内部结构的应用的操作模式设定电路。

公开(公告)号：US5815462A

公开(公告)日：1998-09-29

申请号：US800905

申请日：1997-02-12

Applicant: Yasuhiro Konishi ,  Hisashi Iwamoto ,  Takashi Araki ,  Yasumitsu Murai ,  Seiji Sawada

Inventor： Yasuhiro Konishi ,  Hisashi Iwamoto ,  Takashi Araki ,  Yasumitsu Murai ,  Seiji Sawada

IPC: G11C11/407 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/409 ,  G11C8/00

CPC classification number: G11C7/225 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/22

Abstract: A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.

Abstract translation: 用于控制外部信号的输入和用于控制内部操作的第一时钟信号和用于控制数据输出的第二时钟信号分别被施加到分离的时钟输入节点。 可以调整相对于第一时钟信号的数据输出定时，从而可以调整时钟存取时间和数据保持时间。 内部数据读取路径被流水线化以包括响应于第一时钟信号的第一传送门，用于传送内部读取数据和第二传送门，响应于第二时钟信号，用于从第一传送门传送内部读取数据，以便通过 输出缓冲区。 提供一种同步半导体存储器件，其能够根据应用和减少时钟存取时间将时钟访问时间和数据保持时间设置在最佳值。

公开(公告)号：US5796669A

公开(公告)日：1998-08-18

申请号：US900123

申请日：1997-07-25

Applicant: Takashi Araki ,  Hisashi Iwamoto ,  Yasuhiro Konishi

Inventor： Takashi Araki ,  Hisashi Iwamoto ,  Yasuhiro Konishi

IPC: G11C11/407 ,  G11C11/406 ,  G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C7/1063

Abstract: Switches (11, 12) select either of refresh address counters (6a, 6b) in accordance with a refresh bank set signal (.phi.REFADD) when a bank refresh signal (.phi.BANKREF) is activated. An internal bank address (int.BA) serves as the refresh bank set signal (.phi.REFADD) to control the switch (12) and the refresh address counter (6a or 6b) designated by the internal bank address (int.BA) performs a count operation in synchronization with a refresh clock (.phi.REFCLK). The switch (11) outputs either of refresh addresses (Ref.Add.sub.-- A , Ref.Add.sub.-- B ) which is updated. With this configuration provided is an SDRAM which allows access to data during a refresh operation.

Abstract translation: 当bank刷新信号（phi BANKREF）被激活时，开关（11,12）根据刷新组设置信号（phi REFADD）来选择刷新地址计数器（6a，6b）。 内部银行地址（int.BA）用作刷新组设置信号（phi REFADD）以控制开关（12），由内部银行地址（int.BA）指定的刷新地址计数器（6a或6b）执行 计数操作与刷新时钟同步（phi REFCLK）。 开关（11）输出更新的刷新地址（Ref.Add-A <0:10>，Ref.Add-B <0:10>）。 提供这种配置是允许在刷新操作期间访问数据的SDRAM。

公开(公告)号：US5708611A

公开(公告)日：1998-01-13

申请号：US801889

申请日：1997-02-18

Applicant: Hisashi Iwamoto ,  Yasuhiro Konishi

Inventor： Hisashi Iwamoto ,  Yasuhiro Konishi

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C8/00

CPC classification number: G11C7/222 ,  G11C11/406 ,  G11C7/1072 ,  G11C7/22

Abstract: A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal clock signal is not required to reduce power consumption.

Abstract translation: DLL电路的刷新控制电路响应自动刷新检测信号AR和自刷新检测信号SR，以禁止对相位比较器和电压控制延迟电路的时钟信号ECLK和RCLK的输入。 可以以不需要内部时钟信号来降低功耗的模式停止DLL电路。

公开(公告)号：US5650968A

公开(公告)日：1997-07-22

申请号：US655322

申请日：1996-05-21

Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC: G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC classification number: G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5623454A

公开(公告)日：1997-04-22

申请号：US599265

申请日：1996-02-09

Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC: G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC classification number: G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5511029A

公开(公告)日：1996-04-23

申请号：US246582

申请日：1994-05-19

Applicant: Seiji Sawada ,  Yasuhiro Konishi

Inventor： Seiji Sawada ,  Yasuhiro Konishi

IPC: G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/26 ,  G11C29/34 ,  G11C29/40 ,  G11C7/00

CPC classification number: G11C29/40 ,  G11C29/26

Abstract: In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression circuit of either a bank #A or a bank #B. A tristate inverter buffer passes the 1-bit compression data selected by the bank selection circuit in accordance with a test mode command signal. The data output terminal outputs compressed data of a plurality of bits of memory cells. Thus, it is possible to simultaneously determine pass/fail of a plurality of memory cells, thereby reducing the test time.

Abstract translation: 为了减少同步型存储器件的测试时间，压缩电路将输入到数据输出端子的多个读寄存器中输入的多个存储单元数据压缩为1位数据。 存储体选择电路选择存储体#A或存储体#B的压缩电路的输出。 三态反相缓冲器根据测试模式命令信号传递由存储体选择电路选择的1位压缩数据。 数据输出端输出多个位的存储单元的压缩数据。 因此，可以同时确定多个存储单元的通过/失败，从而减少测试时间。

公开(公告)号：US5184321A

公开(公告)日：1993-02-02

申请号：US821875

申请日：1992-01-16

Applicant: Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

Inventor： Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

IPC: G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4074 ,  G11C11/408 ,  Y10S257/92

Abstract: A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.

Abstract translation: 多个存储器阵列（10a，10b）形成在半导体芯片（CH）上。 外围电路（60）布置在多个存储器阵列（10a，10b）的中心部分。 在半导体芯片（CH）的两端形成有多个焊盘（PD; p1差异p18）。 多个存储器阵列（10a，10b）由预定层形成（101差异109）。 要连接在多个焊盘（PD; p1 DIFFERENCE p18）和外围电路（60）之间的多个互连（L）被设置成跨越多个存储器阵列。 多个互连（L）由除预定的互连层之外的层（112; 113）形成。

公开(公告)号：US4961167A

公开(公告)日：1990-10-02

申请号：US381347

申请日：1989-07-18

Applicant: Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

Inventor： Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

IPC: G11C11/4074

CPC classification number: G11C11/4074

Abstract: A dynamic random access memory with self-refresh function, which includes a substrate bias generator (100) adapted to be intermittently driven to apply a bias potential to a semiconductor substrate (15). This memory device comprises a circuit (91) for generating an internal refresh instruction signal (.phi..sub.S) in response to an external refresh instruction signal, a circuit (92, 93) which, in response to the internal refresh instruction signal, generates a refresh enable signal (.phi..sub.R) intermittently at a predetermined interval, a circuit (94, 95, 96, 98) which, in response to the refresh enable signal, refreshes data in the memory cells, and a circuit (99) which, in response to the internal refresh instruction signal and refresh enable signal, activates the substrate bias generator in the same cycle as the cycle of generation of the refresh enable signal and only for a time shorter than the cycle of generation of the refresh enable signal. The above construction contributes to a reduced power consumption in the dynamic random access memory.

Abstract translation: 一种具有自刷新功能的动态随机存取存储器，其包括适于被间歇地驱动以向半导体衬底（15）施加偏置电位的衬底偏置发生器（100）。 该存储装置包括用于响应于外部刷新指令信号产生内部刷新指令信号（phi S）的电路（91），响应于内部刷新指令信号产生刷新的电路（92,93） 使能信号（phi R）以预定的间隔间歇地连接到响应于刷新使能信号刷新存储器单元中的数据的电路（94,95,96,98）和响应于电路（99）的电路（99） 对于内部刷新指令信号和刷新使能信号，在与产生刷新使能信号的周期相同的周期中，仅在比生成刷新使能信号的周期短的时间内激活衬底偏置发生器。 上述结构有助于动态随机存取存储器中的功耗降低。