公开(公告)号：US20180375519A1

公开(公告)日：2018-12-27

申请号：US15634183

申请日：2017-06-27

Applicant: Intel IP Corporation

Inventor： Michael Kerner ,  Elan Banin ,  Yair Dgani ,  Evgeny Shumaker ,  Danniel Nahmanny ,  Gil Horovitz

IPC: H03L7/087

Abstract: Systems, methods, and circuitries for synchronizing a first phase locked loop (PLL) with a second PLL are provided. In one example a PLL system includes a first PLL configured to generate a first signal; a second PLL configured to generate a second signal; and phase calculation circuitry. The phase calculation circuitry is configured to calculate a phase of the first signal at a given time; and provide the calculated phase to the second PLL for use by the second PLL in synchronizing a phase of the second with the phase of the first signal.

公开(公告)号：US20180331878A1

公开(公告)日：2018-11-15

申请号：US15775845

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Itay Almog ,  Michael Kerner

IPC: H04L27/34 ,  H04L27/36 ,  H04L27/26

Abstract: A communication device is provided that includes a modulation circuit configured to modulate a signal comprising a first signal portion of a first data type and a second signal portion of a second data type. The modulation circuit is configured to modulate the first signal portion in accordance with a first modulation scheme and the second signal portion in accordance with a second modulation scheme. At least one of the first data type is different from the second data type or the second modulation scheme is different from the first modulation scheme. The communication device further includes a modification circuit configured to modify the modulated first signal portion based on a first modification scheme and the second signal portion based on a second modification scheme. The communication device further includes a transmitter configured to transmit the modified first signal portion and the modified second signal portion.

公开(公告)号：US20180159566A1

公开(公告)日：2018-06-07

申请号：US15371768

申请日：2016-12-07

Applicant: Intel IP Corporation

Inventor： Nati Dinur ,  Uri Perlmutter ,  Michael Kerner

IPC: H04B1/04 ,  H04L27/26 ,  H04L27/32

CPC classification number: H04B1/0475 ,  H03F1/025 ,  H03F1/3241 ,  H03F3/189 ,  H04B2001/0408 ,  H04L27/2626 ,  H04L27/32

Abstract: An envelope tracking arrangement is disclosed and includes a level select component, a chunk supply component and a power amplifier. The level select component is configured to segment an input signal into chunks based on time and to select a chunk level for each chunk based on information or envelope information. The chunk supply component is configured to selectively provide a discrete supply voltage according to the selected chunk level. The power amplifier is configured to generate a radio frequency (RF) output signal based on the input signal and utilizing the discrete supply voltage.

公开(公告)号：US20170353163A1

公开(公告)日：2017-12-07

申请号：US15584076

申请日：2017-05-02

Applicant: Intel IP Corporation

Inventor： Avi Gazneli ,  Michael Kerner ,  Amir Rubin ,  ltay Almog ,  Avi Sulimarski

IPC: H03F1/32 ,  H03F3/20

CPC classification number: H03F1/3247 ,  H03F1/30 ,  H03F1/3258 ,  H03F3/195 ,  H03F3/20 ,  H03F3/245 ,  H03F2200/102 ,  H03F2200/105 ,  H03F2200/294 ,  H03F2200/447 ,  H03F2200/465 ,  H03F2200/468 ,  H03F2201/3224 ,  H03F2201/3233

Abstract: A method for predistorting an input signal of an amplifier device comprises evaluating a selection criterion for a computational model of the amplifier device. The computational model provides an output signal of the amplifier device for the input signal of the amplifier device. Further, the method comprises selecting between a first computational model of the amplifier device and a second computational model of the amplifier device based on the evaluated selection criterion. Additionally, the method comprises predistorting the input signal of the amplifier device using the selected computational model.

公开(公告)号：US20170288851A1

公开(公告)日：2017-10-05

申请号：US15088388

申请日：2016-04-01

Applicant: Intel IP Corporation

Inventor： Rotem Avivi ,  Michael Kerner

IPC: H04L7/033 ,  H04B15/02

CPC classification number: H04L7/0331 ,  H03L7/093 ,  H03L2207/50 ,  H04B15/02

Abstract: Embodiments related to systems, methods, and computer-readable media to enable a digital phase locked loop are described. In one embodiment, a digital synthesizer comprises a digital phase locked loop with detection circuitry to calculate an estimate of a magnitude and a phase of a spurious response from an error signal within the digital phase locked loop. The digital phase locked loop further comprises generation circuitry to generate an inverse spur based on the estimate of the magnitude and the phase, and further comprises injection circuitry to inject the inverse spur into the digital phase locked loop. In some embodiments, least mean squares (LMS), recursive least squares (RLS), or other such adaptation is used to estimate the magnitude and phase of the spurious response.