公开(公告)号：US10914618B2

公开(公告)日：2021-02-09

申请号：US15851609

申请日：2017-12-21

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Ya-Wen Yang ,  Kuan-Wei Chen ,  Shyh-Shyuan Sheu

IPC: G01D18/00 ,  G01D3/02

Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.

公开(公告)号：US20210004678A1

公开(公告)日：2021-01-07

申请号：US16846427

申请日：2020-04-13

Applicant: Industrial Technology Research Institute

Inventor： Shih-Chieh Chang ,  Sih-Han Li ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Heng-Yuan Lee

IPC: G06N3/08 ,  G11C11/54 ,  G06N3/04

Abstract: A neural circuit is provided. The neural circuit includes a neural array. The neural array includes a plurality of semiconductor components. Each of the semiconductor components stores a weighting value to generate a corresponding output current or a corresponding equivalent resistance. The neural array receives a plurality of input signals to control the semiconductor components in the neural array and respectively generates the output currents or changes the equivalent resistances. Since the semiconductor components are coupled to each other, output of the neural array may generate a summation current or a summation equivalent resistance related to the input signals and a weighting condition, so that a computing result exhibits high performance.

公开(公告)号：US20230153375A1

公开(公告)日：2023-05-18

申请号：US18155762

申请日：2023-01-18

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G06F17/16 ,  G11C11/412

CPC classification number: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

公开(公告)号：US20220413801A1

公开(公告)日：2022-12-29

申请号：US17679090

申请日：2022-02-24

Applicant: Industrial Technology Research Institute

Inventor： Jian-Wei Su ,  Chih-Sheng Lin ,  Peng-I Mei ,  Sih-Han Li ,  Shyh-Shyuan Sheu ,  Jheng Yang Dai

IPC: G06F7/523 ,  G06F7/50

Abstract: A configurable computing unit within memory including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor is provided. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first readout bit line and a common signal line. The first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first readout bit line and the common signal line. The second input transistor is coupled to a second input bit line, and the second weight transistor receives the second weight bit.

公开(公告)号：US11280641B2

公开(公告)日：2022-03-22

申请号：US16426203

申请日：2019-05-30

Applicant: Industrial Technology Research Institute

Inventor： Chang-Po Chao ,  Wen-Yu Chen ,  Tsai-Kan Chien ,  Sih-Han Li

IPC: G01D5/244

Abstract: A position-encoding device includes a sensing device, a filtering device, a calibrating device and a compensating device. The sensing device senses the motion of a moving device to generate first and second signals. The filtering device filters the first and second signals to generate first and second filtering signal. The calibrating device captures the first and second filtering signals to obtain time and phase information of the first and second filtering signals, performs gain and offset calibration on the first and second filtering signals, and performs a phase calibration on the first and second filtering signals through first, second feedback signals and the time and phase information of the first and second filtering signals to generate first and second calibrating signals. The compensating device compensates for the first and second calibrating signals according to a lookup table, so as to generate first and second position encoding signals.

公开(公告)号：US20190079039A1

公开(公告)日：2019-03-14

申请号：US16178599

申请日：2018-11-02

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Kuan-Wei Chen ,  Erh-Hao Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

Abstract: A method of manufacturing a sensor device is provided. In the method, sensing electrodes are formed on a substrate, a sensing material layer is formed on the sensing electrodes. The sensing material layer is etched to form a first nanowire sensing region, a second nanowire sensing region and a third nanowire sensing region respectively between every two sensing electrodes of the sensing electrodes. A dielectric layer is formed to cover the first nanowire sensing region, the second nanowire sensing region and the third nanowire sensing region, and the first nanowire sensing region and the third nanowire sensing region are exposed.

公开(公告)号：US20180238822A1

公开(公告)日：2018-08-23

申请号：US15955691

申请日：2018-04-18

Applicant: Industrial Technology Research Institute

Inventor： Kuan-Wei Chen ,  Chih-Sheng Lin ,  Erh-Hao Chen ,  Sih-Han Li ,  Shyh-Shyuan Sheu

IPC: G01N27/12

CPC classification number: G01N27/127 ,  G01N27/122 ,  G01N33/0031

Abstract: A gas sensing apparatus including a gas sensor, a gas determining circuit and a gas database is provided. The gas sensor includes at least two nanowire sensors. The gas sensor is configured to sense multiple gases and output a plurality of sensing signals. The gas determining circuit is coupled to the gas sensor. The gas determining circuit is configured to receive the sensing signals and determine types of the gases according to reference data and the sensing signals. The gas database is coupled to the gas determining circuit. The gas database stores the reference data and outputs the reference data to the gas determining circuit. Each of the nanowire sensors includes at least one nanowire. Structural properties of the nanowires are different.

公开(公告)号：US09378785B2

公开(公告)日：2016-06-28

申请号：US13974001

申请日：2013-08-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chih-He Lin ,  Sih-Han Li ,  Wen-Pin Lin ,  Shyh-Shyuan Sheu

IPC: G11C11/00 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C7/1072 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2013/0076

Abstract: A resistive random-access memory device includes a memory array, a read circuit, a write-back logic circuit and a write-back circuit. The read circuit reads the data stored in a selected memory cell and accordingly generates a first control signal. The write-back logic circuit generates a write-back control signal according to the first control signal and a second control signal. The write-back circuit performs a write-back operation on the selected memory cell according to the write-back control signal and a write-back voltage, so as to change a resistance state of the selected memory cell from a low resistance state to a high resistance state, and generates the second control signal according to the resistance state of the selected memory cell.

Abstract translation: 电阻式随机存取存储器件包括存储器阵列，读取电路，回写逻辑电路和回写电路。 读取电路读取存储在所选择的存储器单元中的数据，并且相应地产生第一控制信号。 回写逻辑电路根据第一控制信号和第二控制信号产生回写控制信号。 回写电路根据回写控制信号和回写电压对所选择的存储单元执行写回操作，以将所选存储单元的电阻状态从低电阻状态改变为 并且根据所选存储单元的电阻状态产生第二控制信号。

公开(公告)号：US09076771B2

公开(公告)日：2015-07-07

申请号：US13974909

申请日：2013-08-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sih-Han Li ,  Pei-Ling Tseng ,  Zhe-Hui Lin ,  Chih-Sheng Lin

IPC: H01L29/93 ,  H01L23/48 ,  H01L27/08 ,  H01L29/94

CPC classification number: H01L23/481 ,  H01L27/0808 ,  H01L29/93 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.

Abstract translation: 提供变容二极管。 衬底包括衬底中的第一表面，第二表面和第一开口以及第二开口。 导电材料填充第一和第二开口，以形成第一贯穿晶片通孔（TWV）和第二通晶片通孔。 第一电容器耦合在第一通晶片通孔和第一端子之间。 第二电容器耦合在第二通晶片通孔和第二端子之间。 第一贯穿晶片通孔和第二贯通晶片通孔之间的耗尽区电容器的电容由施加到第一贯穿晶片通孔和第二贯通晶片通孔的偏置电压决定。